Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22520326	1		T14	84		T23	11		T24	19
full_word	7550321	1		T14	58		T23	1		T24	2368

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30070347	1		T14	142		T23	12		T24	2387
auto[TlIntgErrCmd]	98	1		T126	9		T209	10		T210	2
auto[TlIntgErrData]	102	1		T126	5		T209	4		T210	6
auto[TlIntgErrBoth]	100	1		T126	6		T209	6		T210	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	25714673	1		T14	77		T23	12		T24	1217
auto[1]	4355974	1		T14	65		T24	1170		T27	65

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21907812	1		T14	63		T23	11		T24	19
auto[TlIntgErrNone]	partial	auto[1]	612235	1		T14	21		T27	16		T29	1153
auto[TlIntgErrNone]	full_word	auto[0]	3806725	1		T14	14		T23	1		T24	1198
auto[TlIntgErrNone]	full_word	auto[1]	3743575	1		T14	44		T24	1170		T27	49
auto[TlIntgErrCmd]	partial	auto[0]	42	1		T126	4		T209	4		T210	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T126	5		T209	3		T210	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T209	2		T317	1		T313	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T209	1		T230	1		T315	2
auto[TlIntgErrData]	partial	auto[0]	43	1		T126	1		T210	3		T233	1
auto[TlIntgErrData]	partial	auto[1]	53	1		T126	3		T209	4		T210	3
auto[TlIntgErrData]	full_word	auto[0]	1	1		T312	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T126	1		T312	1		T318	2
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T126	2		T209	4		T210	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T126	2		T209	2		T210	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T126	1		T319	1		T317	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T126	1		T320	1		T321	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23214	1		T29	1084		T25	886		T126	14
full_word	4341566	1		T29	475		T25	476		T126	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4364503	1		T29	1559		T25	1362		T118	226
auto[TlIntgErrCmd]	72	1		T126	5		T209	3		T210	1
auto[TlIntgErrData]	105	1		T126	6		T209	5		T210	4
auto[TlIntgErrBoth]	100	1		T126	4		T209	11		T210	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4335762	1		T29	59		T25	103		T126	6
auto[1]	29018	1		T29	1500		T25	1259		T126	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1515	1		T29	52		T25	93		T118	7
auto[TlIntgErrNone]	partial	auto[1]	21443	1		T29	1032		T25	793		T118	168
auto[TlIntgErrNone]	full_word	auto[0]	4334143	1		T29	7		T25	10		T118	1
auto[TlIntgErrNone]	full_word	auto[1]	7402	1		T29	468		T25	466		T118	50
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T126	2		T209	1		T230	1
auto[TlIntgErrCmd]	partial	auto[1]	41	1		T126	3		T209	2		T233	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T318	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T210	1		T313	1		T314	1
auto[TlIntgErrData]	partial	auto[0]	37	1		T126	3		T210	3		T233	1
auto[TlIntgErrData]	partial	auto[1]	58	1		T126	2		T209	4		T210	1
auto[TlIntgErrData]	full_word	auto[0]	6	1		T233	1		T232	1		T312	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T126	1		T209	1		T230	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T126	1		T209	4		T210	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T126	3		T209	5		T210	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T322	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T209	2		T320	2		T322	1