Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_phy
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.26 97.67 85.11 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash 94.26 97.67 85.11 100.00


Module Instance : tb.dut.u_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.26 97.67 85.11 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.86 98.42 93.44 99.62 97.62 99.60 98.44


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.36 97.14 92.91 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flash_cores[0].u_core 98.29 98.00 94.09 100.00 100.00 99.66 97.98
gen_flash_cores[0].u_host_rsp_fifo 97.84 100.00 89.19 100.00 100.00 100.00
gen_flash_cores[1].u_core 97.79 98.00 92.45 98.97 100.00 99.31 97.98
gen_flash_cores[1].u_host_rsp_fifo 96.76 100.00 83.78 100.00 100.00 100.00
u_bank_sequence_fifo 95.19 100.00 80.77 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_flash 97.84 98.77 94.86 100.00 93.75 99.67 100.00
u_lc_nvm_debug_en_sync 100.00 100.00 100.00 100.00
u_region_sel 100.00 100.00 100.00 100.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_phy
Line No.TotalCoveredPercent
TOTAL434297.67
CONT_ASSIGN11711100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN12511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN12900
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13511100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13711100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14211100.00
CONT_ASSIGN14311100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN18911100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19711100.00
CONT_ASSIGN20511100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN22311100.00
CONT_ASSIGN24711100.00
CONT_ASSIGN24711100.00
CONT_ASSIGN24811100.00
CONT_ASSIGN24811100.00
CONT_ASSIGN31100
CONT_ASSIGN32711100.00
CONT_ASSIGN36811100.00
CONT_ASSIGN371100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
117 1 1
118 1 1
121 1 1
124 1 1
125 1 1
126 1 1
129 unreachable
130 1 1
131 1 1
132 1 1
133 1 1
134 1 1
135 1 1
136 1 1
137 1 1
138 1 1
139 1 1
140 1 1
141 1 1
142 1 1
143 1 1
174 9 9
189 1 1
195 1 1
197 1 1
205 1 1
206 1 1
223 2 2
247 2 2
248 2 2
311 unreachable
327 1 1
368 1 1
371 0 1

Cond Coverage for Module : flash_phy
TotalCoveredPercent
Conditions474085.11
Logical474085.11
Non-Logical00
Event00

 LINE       117
 EXPRESSION (host_req_i ? host_addr_i[(flash_ctrl_pkg::BusAddrW - 1)-:flash_ctrl_pkg::BankW] : '0)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5 

 LINE       121
 EXPRESSION (host_req_rdy[host_bank_sel] & host_rsp_avail[host_bank_sel] & seq_fifo_rdy)
             -------------1-------------   --------------2--------------   ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T3,T5 

 LINE       124
 EXPRESSION (seq_fifo_pending & host_rsp_vld[rsp_bank_sel])
             --------1-------   -------------2------------
-1--2-StatusTests
01CoveredT16,T77,T32
10CoveredT1,T3,T5
11CoveredT1,T3,T5 

 LINE       151
 EXPRESSION (host_req_i & host_req_rdy_o)
             -----1----   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT3,T5,T6
11CoveredT1,T3,T5 

 LINE       223
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 0))
             -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T5,T6
11CoveredT1,T3,T5 

 LINE       223
 SUB-EXPRESSION (rsp_bank_sel == 0)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       223
 EXPRESSION (host_req_done_o & (rsp_bank_sel == 1))
             -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT3,T5,T6
10CoveredT1,T3,T5
11CoveredT3,T5,T6 

 LINE       223
 SUB-EXPRESSION (rsp_bank_sel == 1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T6 

 LINE       247
 EXPRESSION (host_req_i & (host_bank_sel == 0) & host_rsp_avail[0])
             -----1----   ----------2---------   --------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T5,T6
110CoveredT3,T6,T51
111CoveredT1,T3,T5 

 LINE       247
 SUB-EXPRESSION (host_bank_sel == 0)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       247
 EXPRESSION (host_req_i & (host_bank_sel == 1) & host_rsp_avail[1])
             -----1----   ----------2---------   --------3--------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T5
110CoveredT3,T6,T46
111CoveredT3,T5,T6 

 LINE       247
 SUB-EXPRESSION (host_bank_sel == 1)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T5,T6 

 LINE       248
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 0))
             --------1-------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       248
 SUB-EXPRESSION (ctrl_bank_sel == 0)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       248
 EXPRESSION (flash_ctrl_i.req & (ctrl_bank_sel == 1))
             --------1-------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       248
 SUB-EXPRESSION (ctrl_bank_sel == 1)
                ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       368
 EXPRESSION (flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack)
             -----------1-----------   -----------2----------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Module : flash_phy
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 117 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	117	(host_req_i) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T5
0 Covered T1,T2,T3

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