Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1602509748	1598894088	0	0
CheckNGreaterZero_A	4220	4220	0	0
GntImpliesReady_A	1602509748	456813622	0	0
GntImpliesValid_A	1602509748	456813622	0	0
GrantKnown_A	1602509748	1598894088	0	0
IdxKnown_A	1602509748	1598894088	0	0
IndexIsCorrect_A	1602509748	456813622	0	0
NoReadyValidNoGrant_A	1602509748	179870834	0	0
Priority_A	1602509748	481273674	0	0
ReadyAndValidImplyGrant_A	1602509748	456813622	0	0
ReqAndReadyImplyGrant_A	1602509748	456813622	0	0
ReqImpliesValid_A	1602509748	481273674	0	0
ValidKnown_A	1602509748	1598894088	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	1598894088	0	0
T1	56084	53148	0	0
T2	12372	12124	0	0
T3	189192	188864	0	0
T4	769040	768772	0	0
T5	491572	490984	0	0
T10	6044	5208	0	0
T11	14700	12144	0	0
T18	7640	7056	0	0
T19	257600	256844	0	0
T20	899916	899576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4220	4220	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0
T20	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	456813622	0	0
T1	56084	2494	0	0
T2	12372	644	0	0
T3	189192	41758	0	0
T4	769040	28734	0	0
T5	491572	65796	0	0
T6	0	133682	0	0
T10	6044	132	0	0
T11	14700	450	0	0
T18	7640	132	0	0
T19	257600	43806	0	0
T20	899916	295346	0	0
T21	0	25540	0	0
T50	0	6	0	0
T51	0	32564	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	456813622	0	0
T1	56084	2494	0	0
T2	12372	644	0	0
T3	189192	41758	0	0
T4	769040	28734	0	0
T5	491572	65796	0	0
T6	0	133682	0	0
T10	6044	132	0	0
T11	14700	450	0	0
T18	7640	132	0	0
T19	257600	43806	0	0
T20	899916	295346	0	0
T21	0	25540	0	0
T50	0	6	0	0
T51	0	32564	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	1598894088	0	0
T1	56084	53148	0	0
T2	12372	12124	0	0
T3	189192	188864	0	0
T4	769040	768772	0	0
T5	491572	490984	0	0
T10	6044	5208	0	0
T11	14700	12144	0	0
T18	7640	7056	0	0
T19	257600	256844	0	0
T20	899916	899576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	1598894088	0	0
T1	56084	53148	0	0
T2	12372	12124	0	0
T3	189192	188864	0	0
T4	769040	768772	0	0
T5	491572	490984	0	0
T10	6044	5208	0	0
T11	14700	12144	0	0
T18	7640	7056	0	0
T19	257600	256844	0	0
T20	899916	899576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	456813622	0	0
T1	56084	2494	0	0
T2	12372	644	0	0
T3	189192	41758	0	0
T4	769040	28734	0	0
T5	491572	65796	0	0
T6	0	133682	0	0
T10	6044	132	0	0
T11	14700	450	0	0
T18	7640	132	0	0
T19	257600	43806	0	0
T20	899916	295346	0	0
T21	0	25540	0	0
T50	0	6	0	0
T51	0	32564	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	179870834	0	0
T1	56084	2796	0	0
T2	12372	390	0	0
T3	189192	63032	0	0
T4	769040	1664	0	0
T5	491572	175814	0	0
T6	0	98226	0	0
T10	6044	528	0	0
T11	14700	1600	0	0
T18	7640	512	0	0
T19	257600	424	0	0
T20	899916	8802	0	0
T21	0	830858	0	0
T50	0	10	0	0
T51	0	304	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	481273674	0	0
T1	56084	2494	0	0
T2	12372	644	0	0
T3	189192	52064	0	0
T4	769040	28734	0	0
T5	491572	68638	0	0
T6	0	181728	0	0
T10	6044	132	0	0
T11	14700	450	0	0
T18	7640	132	0	0
T19	257600	43806	0	0
T20	899916	295346	0	0
T21	0	290730	0	0
T50	0	6	0	0
T51	0	32564	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	456813622	0	0
T1	56084	2494	0	0
T2	12372	644	0	0
T3	189192	41758	0	0
T4	769040	28734	0	0
T5	491572	65796	0	0
T6	0	133682	0	0
T10	6044	132	0	0
T11	14700	450	0	0
T18	7640	132	0	0
T19	257600	43806	0	0
T20	899916	295346	0	0
T21	0	25540	0	0
T50	0	6	0	0
T51	0	32564	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	456813622	0	0
T1	56084	2494	0	0
T2	12372	644	0	0
T3	189192	41758	0	0
T4	769040	28734	0	0
T5	491572	65796	0	0
T6	0	133682	0	0
T10	6044	132	0	0
T11	14700	450	0	0
T18	7640	132	0	0
T19	257600	43806	0	0
T20	899916	295346	0	0
T21	0	25540	0	0
T50	0	6	0	0
T51	0	32564	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	481273674	0	0
T1	56084	2494	0	0
T2	12372	644	0	0
T3	189192	52064	0	0
T4	769040	28734	0	0
T5	491572	68638	0	0
T6	0	181728	0	0
T10	6044	132	0	0
T11	14700	450	0	0
T18	7640	132	0	0
T19	257600	43806	0	0
T20	899916	295346	0	0
T21	0	290730	0	0
T50	0	6	0	0
T51	0	32564	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1602509748	1598894088	0	0
T1	56084	53148	0	0
T2	12372	12124	0	0
T3	189192	188864	0	0
T4	769040	768772	0	0
T5	491572	490984	0	0
T10	6044	5208	0	0
T11	14700	12144	0	0
T18	7640	7056	0	0
T19	257600	256844	0	0
T20	899916	899576	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400627437	399723522	0	0
CheckNGreaterZero_A	1055	1055	0	0
GntImpliesReady_A	400627437	122972007	0	0
GntImpliesValid_A	400627437	122972007	0	0
GrantKnown_A	400627437	399723522	0	0
IdxKnown_A	400627437	399723522	0	0
IndexIsCorrect_A	400627437	122972007	0	0
NoReadyValidNoGrant_A	400627437	46517566	0	0
Priority_A	400627437	129126199	0	0
ReadyAndValidImplyGrant_A	400627437	122972007	0	0
ReqAndReadyImplyGrant_A	400627437	122972007	0	0
ReqImpliesValid_A	400627437	129126199	0	0
ValidKnown_A	400627437	399723522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122972007	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122972007	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122972007	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	46517566	0	0
T1	14021	1391	0	0
T2	3093	144	0	0
T3	47298	16965	0	0
T4	192260	832	0	0
T5	122893	43642	0	0
T10	1511	264	0	0
T11	3675	800	0	0
T18	1910	256	0	0
T19	64400	170	0	0
T20	224979	1903	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	129126199	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	13494	0	0
T4	192260	14367	0	0
T5	122893	16758	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122972007	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122972007	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	129126199	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	13494	0	0
T4	192260	14367	0	0
T5	122893	16758	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400627437	399723522	0	0
CheckNGreaterZero_A	1055	1055	0	0
GntImpliesReady_A	400627437	122951123	0	0
GntImpliesValid_A	400627437	122951123	0	0
GrantKnown_A	400627437	399723522	0	0
IdxKnown_A	400627437	399723522	0	0
IndexIsCorrect_A	400627437	122951123	0	0
NoReadyValidNoGrant_A	400627437	46517568	0	0
Priority_A	400627437	129105313	0	0
ReadyAndValidImplyGrant_A	400627437	122951123	0	0
ReqAndReadyImplyGrant_A	400627437	122951123	0	0
ReqImpliesValid_A	400627437	129105313	0	0
ValidKnown_A	400627437	399723522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122951123	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122951123	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122951123	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	46517568	0	0
T1	14021	1391	0	0
T2	3093	144	0	0
T3	47298	16965	0	0
T4	192260	832	0	0
T5	122893	43642	0	0
T10	1511	264	0	0
T11	3675	800	0	0
T18	1910	256	0	0
T19	64400	170	0	0
T20	224979	1903	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	129105313	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	13494	0	0
T4	192260	14367	0	0
T5	122893	16758	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122951123	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	122951123	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	11014	0	0
T4	192260	14367	0	0
T5	122893	16326	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	129105313	0	0
T1	14021	983	0	0
T2	3093	42	0	0
T3	47298	13494	0	0
T4	192260	14367	0	0
T5	122893	16758	0	0
T10	1511	66	0	0
T11	3675	225	0	0
T18	1910	66	0	0
T19	64400	13445	0	0
T20	224979	128835	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400627437	399723522	0	0
CheckNGreaterZero_A	1055	1055	0	0
GntImpliesReady_A	400627437	105445246	0	0
GntImpliesValid_A	400627437	105445246	0	0
GrantKnown_A	400627437	399723522	0	0
IdxKnown_A	400627437	399723522	0	0
IndexIsCorrect_A	400627437	105445246	0	0
NoReadyValidNoGrant_A	400627437	43417850	0	0
Priority_A	400627437	111521081	0	0
ReadyAndValidImplyGrant_A	400627437	105445246	0	0
ReqAndReadyImplyGrant_A	400627437	105445246	0	0
ReqImpliesValid_A	400627437	111521081	0	0
ValidKnown_A	400627437	399723522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	43417850	0	0
T1	14021	7	0	0
T2	3093	51	0	0
T3	47298	14551	0	0
T4	192260	0	0	0
T5	122893	44265	0	0
T6	0	49113	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	42	0	0
T20	224979	2498	0	0
T21	0	415429	0	0
T50	0	5	0	0
T51	0	152	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	111521081	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	12538	0	0
T4	192260	0	0	0
T5	122893	17561	0	0
T6	0	90864	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	145365	0	0
T50	0	3	0	0
T51	0	16282	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	111521081	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	12538	0	0
T4	192260	0	0	0
T5	122893	17561	0	0
T6	0	90864	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	145365	0	0
T50	0	3	0	0
T51	0	16282	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	400627437	399723522	0	0
CheckNGreaterZero_A	1055	1055	0	0
GntImpliesReady_A	400627437	105445246	0	0
GntImpliesValid_A	400627437	105445246	0	0
GrantKnown_A	400627437	399723522	0	0
IdxKnown_A	400627437	399723522	0	0
IndexIsCorrect_A	400627437	105445246	0	0
NoReadyValidNoGrant_A	400627437	43417850	0	0
Priority_A	400627437	111521081	0	0
ReadyAndValidImplyGrant_A	400627437	105445246	0	0
ReqAndReadyImplyGrant_A	400627437	105445246	0	0
ReqImpliesValid_A	400627437	111521081	0	0
ValidKnown_A	400627437	399723522	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1055	1055	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	43417850	0	0
T1	14021	7	0	0
T2	3093	51	0	0
T3	47298	14551	0	0
T4	192260	0	0	0
T5	122893	44265	0	0
T6	0	49113	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	42	0	0
T20	224979	2498	0	0
T21	0	415429	0	0
T50	0	5	0	0
T51	0	152	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	111521081	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	12538	0	0
T4	192260	0	0	0
T5	122893	17561	0	0
T6	0	90864	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	145365	0	0
T50	0	3	0	0
T51	0	16282	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	105445246	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	9865	0	0
T4	192260	0	0	0
T5	122893	16572	0	0
T6	0	66841	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	12770	0	0
T50	0	3	0	0
T51	0	16282	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	111521081	0	0
T1	14021	264	0	0
T2	3093	280	0	0
T3	47298	12538	0	0
T4	192260	0	0	0
T5	122893	17561	0	0
T6	0	90864	0	0
T10	1511	0	0	0
T11	3675	0	0	0
T18	1910	0	0	0
T19	64400	8458	0	0
T20	224979	18838	0	0
T21	0	145365	0	0
T50	0	3	0	0
T51	0	16282	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	400627437	399723522	0	0
T1	14021	13287	0	0
T2	3093	3031	0	0
T3	47298	47216	0	0
T4	192260	192193	0	0
T5	122893	122746	0	0
T10	1511	1302	0	0
T11	3675	3036	0	0
T18	1910	1764	0	0
T19	64400	64211	0	0
T20	224979	224894	0	0