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 LINE       12824
 EXPRESSION (addr_hit[94] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T23,T24
1	0	1	Covered	T14,T24,T29
1	1	0	Not Covered
1	1	1	Covered	T24,T25,T26

 LINE       12825
 EXPRESSION (addr_hit[95] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T24,T27
1	0	1	Covered	T24,T29,T25
1	1	0	Covered	T29,T257,T259
1	1	1	Covered	T24,T25,T26

 LINE       12842
 EXPRESSION (addr_hit[99] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T24,T27
1	0	1	Covered	T24,T29,T25
1	1	0	Covered	T125,T258,T257
1	1	1	Covered	T24,T25,T26

 LINE       12847
 EXPRESSION (addr_hit[102] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T24,T27
1	0	1	Covered	T14,T24,T29
1	1	0	Covered	T125,T130,T257
1	1	1	Not Covered

 LINE       12852
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T24,T27
1	0	1	Covered	T24,T29,T25
1	1	0	Covered	T29,T233,T130
1	1	1	Covered	T24,T25,T26

 LINE       12855
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T24,T27
1	0	1	Covered	T14,T24,T29
1	1	0	Covered	T263,T262,T267
1	1	1	Covered	T24,T25,T26

 LINE       12860
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T24,T27
1	0	1	Covered	T14,T24,T29
1	1	0	Covered	T29,T130,T231
1	1	1	Covered	T24,T25,T26

 LINE       12863
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T14,T23,T24
1	0	1	Covered	T14,T24,T29
1	1	0	Not Covered
1	1	1	Covered	T24,T25,T26

 LINE       13724
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T14,T23,T24