Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403309349	37205752	0	0
DepthKnown_A	403309349	402320946	0	0
RvalidKnown_A	403309349	402320946	0	0
WreadyKnown_A	403309349	402320946	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	37205752	0	0
T14	1468	142	0	0
T23	1202	12	0	0
T24	15630	2600	0	0
T25	3204	2091	0	0
T26	5843	4308	0	0
T27	1339	142	0	0
T28	988	13	0	0
T29	5221	4073	0	0
T30	1322	124	0	0
T31	1257	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T14	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403309349	40923424	0	0
DepthKnown_A	403309349	402320946	0	0
RvalidKnown_A	403309349	402320946	0	0
WreadyKnown_A	403309349	402320946	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	40923424	0	0
T14	1468	142	0	0
T23	1202	62	0	0
T24	15630	2387	0	0
T25	3204	1124	0	0
T26	5843	2289	0	0
T27	1339	142	0	0
T28	988	47	0	0
T29	5221	2089	0	0
T30	1322	124	0	0
T31	1257	77	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T14	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403309349	7868668	0	0
DepthKnown_A	403309349	402320946	0	0
RvalidKnown_A	403309349	402320946	0	0
WreadyKnown_A	403309349	402320946	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	7868668	0	0
T25	3204	233	0	0
T26	5843	0	0	0
T29	5221	637	0	0
T30	1322	0	0	0
T31	1257	0	0	0
T118	4359	230	0	0
T119	3136	62	0	0
T120	0	88	0	0
T121	0	78	0	0
T122	0	67	0	0
T123	0	117	0	0
T124	0	99	0	0
T125	0	100	0	0
T126	79567	0	0	0
T127	1546	0	0	0
T128	309115	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T14	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	403309349	3441770	0	0
DepthKnown_A	403309349	402320946	0	0
RvalidKnown_A	403309349	402320946	0	0
WreadyKnown_A	403309349	402320946	0	0
gen_passthru_fifo.paramCheckPass	1270	1270	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	3441770	0	0
T25	3204	136	0	0
T26	5843	0	0	0
T29	5221	528	0	0
T30	1322	0	0	0
T31	1257	0	0	0
T118	4359	622	0	0
T119	3136	161	0	0
T120	0	55	0	0
T121	0	77	0	0
T122	0	34	0	0
T123	0	363	0	0
T124	0	77	0	0
T125	0	99	0	0
T126	79567	0	0	0
T127	1546	0	0	0
T128	309115	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	403309349	402320946	0	0
T14	1468	1378	0	0
T23	1202	1116	0	0
T24	15630	15530	0	0
T25	3204	3103	0	0
T26	5843	5773	0	0
T27	1339	1288	0	0
T28	988	918	0	0
T29	5221	5149	0	0
T30	1322	1232	0	0
T31	1257	1191	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270	1270	0	0
T14	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0