| T1045 |
/workspace/coverage/default/8.flash_ctrl_prog_reset.3304932924 |
|
|
Dec 24 01:48:53 PM PST 23 |
Dec 24 01:49:08 PM PST 23 |
139965100 ps |
| T1046 |
/workspace/coverage/default/33.flash_ctrl_hw_sec_otp.56159658 |
|
|
Dec 24 01:51:56 PM PST 23 |
Dec 24 01:54:17 PM PST 23 |
9570064400 ps |
| T1047 |
/workspace/coverage/default/62.flash_ctrl_connect.724477571 |
|
|
Dec 24 01:52:47 PM PST 23 |
Dec 24 01:53:10 PM PST 23 |
16577000 ps |
| T1048 |
/workspace/coverage/default/29.flash_ctrl_hw_sec_otp.664052395 |
|
|
Dec 24 01:51:20 PM PST 23 |
Dec 24 01:53:36 PM PST 23 |
1899143500 ps |
| T1049 |
/workspace/coverage/default/39.flash_ctrl_hw_sec_otp.2388492175 |
|
|
Dec 24 01:51:58 PM PST 23 |
Dec 24 01:53:21 PM PST 23 |
3909889500 ps |
| T1050 |
/workspace/coverage/default/2.flash_ctrl_rma_err.655285595 |
|
|
Dec 24 01:47:51 PM PST 23 |
Dec 24 02:01:27 PM PST 23 |
83832429800 ps |
| T1051 |
/workspace/coverage/default/69.flash_ctrl_otp_reset.1645375118 |
|
|
Dec 24 01:52:45 PM PST 23 |
Dec 24 01:54:58 PM PST 23 |
38371400 ps |
| T1052 |
/workspace/coverage/default/12.flash_ctrl_otp_reset.3695441767 |
|
|
Dec 24 01:49:46 PM PST 23 |
Dec 24 01:51:41 PM PST 23 |
38717600 ps |
| T1053 |
/workspace/coverage/default/3.flash_ctrl_phy_arb_redun.4030052169 |
|
|
Dec 24 01:48:07 PM PST 23 |
Dec 24 01:48:28 PM PST 23 |
114637800 ps |
| T1054 |
/workspace/coverage/default/18.flash_ctrl_alert_test.3889233894 |
|
|
Dec 24 01:51:01 PM PST 23 |
Dec 24 01:51:15 PM PST 23 |
52465400 ps |
| T1055 |
/workspace/coverage/default/1.flash_ctrl_rw_evict.1250608177 |
|
|
Dec 24 01:47:37 PM PST 23 |
Dec 24 01:48:09 PM PST 23 |
34311800 ps |
| T1056 |
/workspace/coverage/default/5.flash_ctrl_connect.4220756071 |
|
|
Dec 24 01:48:29 PM PST 23 |
Dec 24 01:48:46 PM PST 23 |
14946000 ps |
| T1057 |
/workspace/coverage/default/18.flash_ctrl_hw_sec_otp.1392607959 |
|
|
Dec 24 01:50:52 PM PST 23 |
Dec 24 01:53:01 PM PST 23 |
3478532200 ps |
| T1058 |
/workspace/coverage/default/13.flash_ctrl_prog_reset.4111996881 |
|
|
Dec 24 01:49:52 PM PST 23 |
Dec 24 01:50:09 PM PST 23 |
42464900 ps |
| T1059 |
/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1194786806 |
|
|
Dec 24 01:48:28 PM PST 23 |
Dec 24 01:56:42 PM PST 23 |
198440370700 ps |
| T1060 |
/workspace/coverage/default/24.flash_ctrl_otp_reset.512680536 |
|
|
Dec 24 01:50:58 PM PST 23 |
Dec 24 01:53:15 PM PST 23 |
71772900 ps |
| T1061 |
/workspace/coverage/default/11.flash_ctrl_otp_reset.1515292331 |
|
|
Dec 24 01:49:38 PM PST 23 |
Dec 24 01:51:54 PM PST 23 |
143441000 ps |
| T1062 |
/workspace/coverage/default/3.flash_ctrl_prog_reset.463750745 |
|
|
Dec 24 01:47:54 PM PST 23 |
Dec 24 01:48:09 PM PST 23 |
40106300 ps |
| T1063 |
/workspace/coverage/default/32.flash_ctrl_rw_evict.3797851613 |
|
|
Dec 24 01:51:52 PM PST 23 |
Dec 24 01:52:25 PM PST 23 |
33874100 ps |
| T1064 |
/workspace/coverage/default/2.flash_ctrl_lcmgr_intg.1995476918 |
|
|
Dec 24 01:48:06 PM PST 23 |
Dec 24 01:48:21 PM PST 23 |
15047300 ps |
| T1065 |
/workspace/coverage/default/1.flash_ctrl_invalid_op.1780258148 |
|
|
Dec 24 01:47:43 PM PST 23 |
Dec 24 01:49:01 PM PST 23 |
6782508700 ps |
| T1066 |
/workspace/coverage/default/2.flash_ctrl_intr_rd.3856466975 |
|
|
Dec 24 01:47:35 PM PST 23 |
Dec 24 01:50:04 PM PST 23 |
2231607500 ps |
| T1067 |
/workspace/coverage/default/26.flash_ctrl_smoke.800262799 |
|
|
Dec 24 01:51:14 PM PST 23 |
Dec 24 01:54:55 PM PST 23 |
54829000 ps |
| T1068 |
/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3624042073 |
|
|
Dec 24 01:51:53 PM PST 23 |
Dec 24 01:55:28 PM PST 23 |
105034914600 ps |
| T1069 |
/workspace/coverage/default/0.flash_ctrl_intr_wr.787601962 |
|
|
Dec 24 01:47:06 PM PST 23 |
Dec 24 01:48:27 PM PST 23 |
6668630700 ps |
| T1070 |
/workspace/coverage/default/36.flash_ctrl_smoke.651078461 |
|
|
Dec 24 01:51:52 PM PST 23 |
Dec 24 01:53:56 PM PST 23 |
61726200 ps |
| T1071 |
/workspace/coverage/default/1.flash_ctrl_hw_rma.1496970126 |
|
|
Dec 24 01:47:07 PM PST 23 |
Dec 24 02:18:04 PM PST 23 |
123492979800 ps |
| T1072 |
/workspace/coverage/default/7.flash_ctrl_rw.100880198 |
|
|
Dec 24 01:48:40 PM PST 23 |
Dec 24 01:57:37 PM PST 23 |
12155405300 ps |
| T1073 |
/workspace/coverage/default/22.flash_ctrl_disable.3991270455 |
|
|
Dec 24 01:50:55 PM PST 23 |
Dec 24 01:51:20 PM PST 23 |
37043000 ps |
| T1074 |
/workspace/coverage/default/1.flash_ctrl_error_prog_win.2637456897 |
|
|
Dec 24 01:46:58 PM PST 23 |
Dec 24 02:01:08 PM PST 23 |
489418200 ps |
| T1075 |
/workspace/coverage/default/37.flash_ctrl_intr_rd.1410154224 |
|
|
Dec 24 01:51:52 PM PST 23 |
Dec 24 01:54:44 PM PST 23 |
2732100100 ps |
| T1076 |
/workspace/coverage/default/10.flash_ctrl_alert_test.200815982 |
|
|
Dec 24 01:49:43 PM PST 23 |
Dec 24 01:50:02 PM PST 23 |
56451400 ps |
| T350 |
/workspace/coverage/default/13.flash_ctrl_disable.550818710 |
|
|
Dec 24 01:49:52 PM PST 23 |
Dec 24 01:50:17 PM PST 23 |
41018000 ps |
| T1077 |
/workspace/coverage/default/3.flash_ctrl_mp_regions.4256928450 |
|
|
Dec 24 01:48:07 PM PST 23 |
Dec 24 01:52:04 PM PST 23 |
15878256100 ps |
| T1078 |
/workspace/coverage/default/20.flash_ctrl_otp_reset.1673702562 |
|
|
Dec 24 01:50:54 PM PST 23 |
Dec 24 01:52:47 PM PST 23 |
40140500 ps |
| T1079 |
/workspace/coverage/default/20.flash_ctrl_prog_reset.4238268370 |
|
|
Dec 24 01:50:54 PM PST 23 |
Dec 24 01:55:52 PM PST 23 |
7647718400 ps |
| T1080 |
/workspace/coverage/default/10.flash_ctrl_ro.1931472756 |
|
|
Dec 24 01:49:36 PM PST 23 |
Dec 24 01:51:30 PM PST 23 |
1476258400 ps |
| T364 |
/workspace/coverage/default/11.flash_ctrl_sec_info_access.1204248588 |
|
|
Dec 24 01:49:42 PM PST 23 |
Dec 24 01:50:57 PM PST 23 |
4120802400 ps |
| T1081 |
/workspace/coverage/default/3.flash_ctrl_hw_sec_otp.1314013310 |
|
|
Dec 24 01:47:52 PM PST 23 |
Dec 24 01:49:43 PM PST 23 |
12781295700 ps |
| T1082 |
/workspace/coverage/default/23.flash_ctrl_connect.1893813054 |
|
|
Dec 24 01:50:56 PM PST 23 |
Dec 24 01:51:15 PM PST 23 |
47547600 ps |
| T1083 |
/workspace/coverage/default/62.flash_ctrl_otp_reset.3493072604 |
|
|
Dec 24 01:52:44 PM PST 23 |
Dec 24 01:54:56 PM PST 23 |
99322700 ps |
| T1084 |
/workspace/coverage/default/2.flash_ctrl_hw_sec_otp.2695510945 |
|
|
Dec 24 01:47:43 PM PST 23 |
Dec 24 01:48:53 PM PST 23 |
2178771900 ps |
| T1085 |
/workspace/coverage/default/28.flash_ctrl_smoke.3574731229 |
|
|
Dec 24 01:51:17 PM PST 23 |
Dec 24 01:54:52 PM PST 23 |
349987900 ps |
| T1086 |
/workspace/coverage/default/19.flash_ctrl_intr_rd.1224441715 |
|
|
Dec 24 01:50:55 PM PST 23 |
Dec 24 01:53:19 PM PST 23 |
1099517100 ps |
| T1087 |
/workspace/coverage/default/0.flash_ctrl_hw_rma_reset.3311512440 |
|
|
Dec 24 01:47:05 PM PST 23 |
Dec 24 01:59:49 PM PST 23 |
40126888200 ps |
| T1088 |
/workspace/coverage/default/9.flash_ctrl_hw_rma_reset.2129190919 |
|
|
Dec 24 01:49:12 PM PST 23 |
Dec 24 02:02:18 PM PST 23 |
240202240600 ps |
| T1089 |
/workspace/coverage/default/43.flash_ctrl_alert_test.734928776 |
|
|
Dec 24 01:52:00 PM PST 23 |
Dec 24 01:52:16 PM PST 23 |
69801700 ps |
| T1090 |
/workspace/coverage/default/4.flash_ctrl_oversize_error.3997117854 |
|
|
Dec 24 01:48:06 PM PST 23 |
Dec 24 01:50:14 PM PST 23 |
1253535400 ps |
| T1091 |
/workspace/coverage/default/49.flash_ctrl_smoke.342266262 |
|
|
Dec 24 01:52:12 PM PST 23 |
Dec 24 01:53:29 PM PST 23 |
22208800 ps |
| T1092 |
/workspace/coverage/default/3.flash_ctrl_serr_counter.4210916942 |
|
|
Dec 24 01:47:51 PM PST 23 |
Dec 24 01:49:06 PM PST 23 |
1248917700 ps |
| T1093 |
/workspace/coverage/default/1.flash_ctrl_re_evict.168248430 |
|
|
Dec 24 01:47:35 PM PST 23 |
Dec 24 01:48:10 PM PST 23 |
206883900 ps |
| T1094 |
/workspace/coverage/default/1.flash_ctrl_smoke.3304566091 |
|
|
Dec 24 01:47:01 PM PST 23 |
Dec 24 01:50:16 PM PST 23 |
42059600 ps |
| T273 |
/workspace/coverage/default/0.flash_ctrl_host_dir_rd.1035835452 |
|
|
Dec 24 01:46:52 PM PST 23 |
Dec 24 01:47:58 PM PST 23 |
69735500 ps |
| T216 |
/workspace/coverage/default/15.flash_ctrl_disable.3572642978 |
|
|
Dec 24 01:50:26 PM PST 23 |
Dec 24 01:50:49 PM PST 23 |
17054300 ps |
| T1095 |
/workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.1435546359 |
|
|
Dec 24 01:48:07 PM PST 23 |
Dec 24 01:48:31 PM PST 23 |
18829500 ps |
| T1096 |
/workspace/coverage/default/14.flash_ctrl_hw_read_seed_err.1938283416 |
|
|
Dec 24 01:50:25 PM PST 23 |
Dec 24 01:50:40 PM PST 23 |
31802700 ps |
| T1097 |
/workspace/coverage/default/4.flash_ctrl_error_prog_type.3246722335 |
|
|
Dec 24 01:47:57 PM PST 23 |
Dec 24 02:28:02 PM PST 23 |
2150561100 ps |
| T1098 |
/workspace/coverage/default/10.flash_ctrl_smoke.4050456835 |
|
|
Dec 24 01:49:25 PM PST 23 |
Dec 24 01:51:06 PM PST 23 |
55326800 ps |
| T1099 |
/workspace/coverage/default/13.flash_ctrl_re_evict.5496463 |
|
|
Dec 24 01:49:48 PM PST 23 |
Dec 24 01:50:26 PM PST 23 |
84981900 ps |
| T1100 |
/workspace/coverage/default/40.flash_ctrl_hw_sec_otp.714072636 |
|
|
Dec 24 01:52:02 PM PST 23 |
Dec 24 01:54:26 PM PST 23 |
3790855500 ps |
| T1101 |
/workspace/coverage/default/4.flash_ctrl_re_evict.1023460242 |
|
|
Dec 24 01:48:11 PM PST 23 |
Dec 24 01:48:43 PM PST 23 |
133318200 ps |
| T1102 |
/workspace/coverage/default/59.flash_ctrl_otp_reset.2135143462 |
|
|
Dec 24 01:52:48 PM PST 23 |
Dec 24 01:55:08 PM PST 23 |
73296300 ps |
| T1103 |
/workspace/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.675677235 |
|
|
Dec 24 01:48:06 PM PST 23 |
Dec 24 01:49:31 PM PST 23 |
10019443800 ps |
| T1104 |
/workspace/coverage/default/29.flash_ctrl_prog_reset.1898657197 |
|
|
Dec 24 01:51:35 PM PST 23 |
Dec 24 01:51:49 PM PST 23 |
64079200 ps |
| T1105 |
/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.2230005523 |
|
|
Dec 24 01:49:52 PM PST 23 |
Dec 24 01:51:11 PM PST 23 |
960764300 ps |
| T1106 |
/workspace/coverage/default/39.flash_ctrl_alert_test.3877590251 |
|
|
Dec 24 01:52:00 PM PST 23 |
Dec 24 01:52:17 PM PST 23 |
153748300 ps |
| T221 |
/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.94525442 |
|
|
Dec 24 01:48:12 PM PST 23 |
Dec 24 01:48:27 PM PST 23 |
38500300 ps |
| T1107 |
/workspace/coverage/default/25.flash_ctrl_connect.2064906381 |
|
|
Dec 24 01:51:15 PM PST 23 |
Dec 24 01:51:32 PM PST 23 |
39879600 ps |
| T1108 |
/workspace/coverage/default/2.flash_ctrl_phy_arb.1333281063 |
|
|
Dec 24 01:47:23 PM PST 23 |
Dec 24 01:49:56 PM PST 23 |
33321300 ps |
| T1109 |
/workspace/coverage/default/12.flash_ctrl_alert_test.3153445514 |
|
|
Dec 24 01:49:47 PM PST 23 |
Dec 24 01:50:04 PM PST 23 |
36644100 ps |
| T38 |
/workspace/coverage/default/0.flash_ctrl_access_after_disable.3662236477 |
|
|
Dec 24 01:46:54 PM PST 23 |
Dec 24 01:47:13 PM PST 23 |
14184700 ps |
| T1110 |
/workspace/coverage/default/34.flash_ctrl_rw_evict.2164488018 |
|
|
Dec 24 01:51:56 PM PST 23 |
Dec 24 01:52:29 PM PST 23 |
52953600 ps |
| T1111 |
/workspace/coverage/default/7.flash_ctrl_ro.1728677751 |
|
|
Dec 24 01:48:33 PM PST 23 |
Dec 24 01:50:02 PM PST 23 |
1539189000 ps |
| T1112 |
/workspace/coverage/default/3.flash_ctrl_rw.4044550818 |
|
|
Dec 24 01:47:52 PM PST 23 |
Dec 24 01:54:50 PM PST 23 |
6235944500 ps |
| T1113 |
/workspace/coverage/default/71.flash_ctrl_connect.1825786363 |
|
|
Dec 24 01:52:47 PM PST 23 |
Dec 24 01:53:05 PM PST 23 |
49883400 ps |
| T1114 |
/workspace/coverage/default/13.flash_ctrl_rw_evict.2040931546 |
|
|
Dec 24 01:49:53 PM PST 23 |
Dec 24 01:50:30 PM PST 23 |
198235300 ps |
| T1115 |
/workspace/coverage/default/3.flash_ctrl_error_prog_type.368978167 |
|
|
Dec 24 01:47:53 PM PST 23 |
Dec 24 02:33:11 PM PST 23 |
3360808900 ps |
| T1116 |
/workspace/coverage/default/3.flash_ctrl_rw_evict_all_en.2324853552 |
|
|
Dec 24 01:47:52 PM PST 23 |
Dec 24 01:48:25 PM PST 23 |
45290800 ps |
| T1117 |
/workspace/coverage/default/1.flash_ctrl_derr_detect.1051773176 |
|
|
Dec 24 01:47:44 PM PST 23 |
Dec 24 01:49:27 PM PST 23 |
125030400 ps |
| T1118 |
/workspace/coverage/default/4.flash_ctrl_phy_arb_redun.2148978767 |
|
|
Dec 24 01:48:11 PM PST 23 |
Dec 24 01:48:26 PM PST 23 |
257416200 ps |
| T1119 |
/workspace/coverage/default/1.flash_ctrl_intr_wr.1592395178 |
|
|
Dec 24 01:47:35 PM PST 23 |
Dec 24 01:49:28 PM PST 23 |
8794253800 ps |
| T1120 |
/workspace/coverage/default/70.flash_ctrl_otp_reset.1260049853 |
|
|
Dec 24 01:52:45 PM PST 23 |
Dec 24 01:54:59 PM PST 23 |
81264000 ps |
| T1121 |
/workspace/coverage/default/4.flash_ctrl_connect.4136371397 |
|
|
Dec 24 01:49:44 PM PST 23 |
Dec 24 01:50:06 PM PST 23 |
13358800 ps |
| T1122 |
/workspace/coverage/default/55.flash_ctrl_connect.2024789382 |
|
|
Dec 24 01:52:33 PM PST 23 |
Dec 24 01:52:52 PM PST 23 |
44764200 ps |
| T1123 |
/workspace/coverage/default/19.flash_ctrl_rw_evict_all_en.1905918280 |
|
|
Dec 24 01:50:54 PM PST 23 |
Dec 24 01:51:30 PM PST 23 |
50690000 ps |
| T1124 |
/workspace/coverage/default/31.flash_ctrl_otp_reset.945966802 |
|
|
Dec 24 01:51:37 PM PST 23 |
Dec 24 01:53:51 PM PST 23 |
38021700 ps |
| T1125 |
/workspace/coverage/default/0.flash_ctrl_write_word_sweep.3138613006 |
|
|
Dec 24 01:46:54 PM PST 23 |
Dec 24 01:47:16 PM PST 23 |
211896900 ps |
| T1126 |
/workspace/coverage/default/3.flash_ctrl_hw_rma_reset.279339265 |
|
|
Dec 24 01:47:54 PM PST 23 |
Dec 24 02:00:49 PM PST 23 |
80149560100 ps |
| T1127 |
/workspace/coverage/default/2.flash_ctrl_smoke.1117194999 |
|
|
Dec 24 01:47:22 PM PST 23 |
Dec 24 01:48:39 PM PST 23 |
32431500 ps |
| T1128 |
/workspace/coverage/default/18.flash_ctrl_invalid_op.4031879827 |
|
|
Dec 24 01:50:51 PM PST 23 |
Dec 24 01:52:20 PM PST 23 |
1013568200 ps |
| T1129 |
/workspace/coverage/default/15.flash_ctrl_sec_info_access.1212620695 |
|
|
Dec 24 01:50:26 PM PST 23 |
Dec 24 01:51:41 PM PST 23 |
1699142300 ps |
| T1130 |
/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.2119793534 |
|
|
Dec 24 01:49:34 PM PST 23 |
Dec 24 01:49:50 PM PST 23 |
26124800 ps |
| T1131 |
/workspace/coverage/default/10.flash_ctrl_intr_rd.3185309340 |
|
|
Dec 24 01:49:37 PM PST 23 |
Dec 24 01:52:27 PM PST 23 |
5158302700 ps |
| T1132 |
/workspace/coverage/default/17.flash_ctrl_connect.351216867 |
|
|
Dec 24 01:50:33 PM PST 23 |
Dec 24 01:50:47 PM PST 23 |
15616800 ps |
| T1133 |
/workspace/coverage/default/44.flash_ctrl_disable.62454735 |
|
|
Dec 24 01:52:40 PM PST 23 |
Dec 24 01:53:04 PM PST 23 |
11844200 ps |
| T1134 |
/workspace/coverage/default/0.flash_ctrl_config_regwen.375930054 |
|
|
Dec 24 01:47:07 PM PST 23 |
Dec 24 01:47:22 PM PST 23 |
70479100 ps |
| T1135 |
/workspace/coverage/default/73.flash_ctrl_otp_reset.2877598900 |
|
|
Dec 24 01:52:44 PM PST 23 |
Dec 24 01:54:56 PM PST 23 |
159453900 ps |
| T1136 |
/workspace/coverage/default/4.flash_ctrl_prog_reset.2584277104 |
|
|
Dec 24 01:48:09 PM PST 23 |
Dec 24 01:48:24 PM PST 23 |
19093500 ps |
| T1137 |
/workspace/coverage/default/14.flash_ctrl_connect.1542368558 |
|
|
Dec 24 01:50:17 PM PST 23 |
Dec 24 01:50:31 PM PST 23 |
16644300 ps |
| T1138 |
/workspace/coverage/default/3.flash_ctrl_ro_serr.1318796338 |
|
|
Dec 24 01:47:53 PM PST 23 |
Dec 24 01:50:02 PM PST 23 |
741228900 ps |
| T1139 |
/workspace/coverage/default/39.flash_ctrl_intr_rd.813123801 |
|
|
Dec 24 01:51:59 PM PST 23 |
Dec 24 01:54:49 PM PST 23 |
2218852200 ps |
| T1140 |
/workspace/coverage/default/26.flash_ctrl_connect.2558091005 |
|
|
Dec 24 01:51:16 PM PST 23 |
Dec 24 01:51:32 PM PST 23 |
62162800 ps |
| T1141 |
/workspace/coverage/default/68.flash_ctrl_connect.669428247 |
|
|
Dec 24 01:52:46 PM PST 23 |
Dec 24 01:53:04 PM PST 23 |
16406100 ps |
| T1142 |
/workspace/coverage/default/4.flash_ctrl_config_regwen.1844186571 |
|
|
Dec 24 01:48:09 PM PST 23 |
Dec 24 01:48:25 PM PST 23 |
23246600 ps |
| T1143 |
/workspace/coverage/default/2.flash_ctrl_derr_detect.3721897601 |
|
|
Dec 24 01:47:34 PM PST 23 |
Dec 24 01:49:21 PM PST 23 |
294237300 ps |
| T1144 |
/workspace/coverage/default/15.flash_ctrl_lcmgr_intg.1080054188 |
|
|
Dec 24 01:50:32 PM PST 23 |
Dec 24 01:50:46 PM PST 23 |
16238300 ps |
| T1145 |
/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.4051507546 |
|
|
Dec 24 01:51:16 PM PST 23 |
Dec 24 01:51:48 PM PST 23 |
111398000 ps |
| T1146 |
/workspace/coverage/default/6.flash_ctrl_invalid_op.584723044 |
|
|
Dec 24 01:48:29 PM PST 23 |
Dec 24 01:49:45 PM PST 23 |
5342356800 ps |
| T1147 |
/workspace/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.2959245590 |
|
|
Dec 24 01:49:35 PM PST 23 |
Dec 24 01:51:44 PM PST 23 |
10012569800 ps |
| T1148 |
/workspace/coverage/default/13.flash_ctrl_lcmgr_intg.3388336789 |
|
|
Dec 24 01:49:52 PM PST 23 |
Dec 24 01:50:10 PM PST 23 |
15515300 ps |
| T1149 |
/workspace/coverage/default/8.flash_ctrl_intr_rd.281573823 |
|
|
Dec 24 01:48:52 PM PST 23 |
Dec 24 01:51:40 PM PST 23 |
4460828000 ps |
| T1150 |
/workspace/coverage/default/29.flash_ctrl_alert_test.2225533272 |
|
|
Dec 24 01:51:56 PM PST 23 |
Dec 24 01:52:12 PM PST 23 |
38279100 ps |
| T1151 |
/workspace/coverage/default/16.flash_ctrl_rand_ops.2761069089 |
|
|
Dec 24 01:50:38 PM PST 23 |
Dec 24 02:06:06 PM PST 23 |
334171900 ps |
| T1152 |
/workspace/coverage/default/13.flash_ctrl_sec_info_access.885103401 |
|
|
Dec 24 01:49:53 PM PST 23 |
Dec 24 01:51:11 PM PST 23 |
14646090300 ps |
| T1153 |
/workspace/coverage/default/11.flash_ctrl_re_evict.3283408911 |
|
|
Dec 24 01:49:37 PM PST 23 |
Dec 24 01:50:16 PM PST 23 |
78466200 ps |
| T1154 |
/workspace/coverage/default/0.flash_ctrl_connect.768345111 |
|
|
Dec 24 01:47:06 PM PST 23 |
Dec 24 01:47:20 PM PST 23 |
28051800 ps |
| T1155 |
/workspace/coverage/default/57.flash_ctrl_otp_reset.371859750 |
|
|
Dec 24 01:52:33 PM PST 23 |
Dec 24 01:54:50 PM PST 23 |
56084300 ps |
| T1156 |
/workspace/coverage/default/1.flash_ctrl_intr_rd.2286586703 |
|
|
Dec 24 01:47:36 PM PST 23 |
Dec 24 01:50:13 PM PST 23 |
4204898100 ps |
| T1157 |
/workspace/coverage/default/14.flash_ctrl_ro.103958112 |
|
|
Dec 24 01:50:19 PM PST 23 |
Dec 24 01:52:02 PM PST 23 |
479354300 ps |
| T1158 |
/workspace/coverage/default/40.flash_ctrl_alert_test.2183756824 |
|
|
Dec 24 01:52:00 PM PST 23 |
Dec 24 01:52:16 PM PST 23 |
44648700 ps |
| T1159 |
/workspace/coverage/default/9.flash_ctrl_re_evict.760940220 |
|
|
Dec 24 01:49:15 PM PST 23 |
Dec 24 01:49:54 PM PST 23 |
522308200 ps |
| T1160 |
/workspace/coverage/default/24.flash_ctrl_alert_test.4065204983 |
|
|
Dec 24 01:51:13 PM PST 23 |
Dec 24 01:51:28 PM PST 23 |
166175100 ps |
| T132 |
/workspace/coverage/default/1.flash_ctrl_phy_ack_consistency.3321306292 |
|
|
Dec 24 01:47:42 PM PST 23 |
Dec 24 01:47:57 PM PST 23 |
25715400 ps |
| T1161 |
/workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.4235331683 |
|
|
Dec 24 01:47:55 PM PST 23 |
Dec 24 02:22:23 PM PST 23 |
856420085500 ps |
| T1162 |
/workspace/coverage/default/30.flash_ctrl_disable.1578801512 |
|
|
Dec 24 01:51:53 PM PST 23 |
Dec 24 01:52:16 PM PST 23 |
15766900 ps |
| T1163 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1464918124 |
|
|
Dec 24 12:41:35 PM PST 23 |
Dec 24 12:41:56 PM PST 23 |
15058600 ps |
| T1164 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.250223013 |
|
|
Dec 24 12:41:10 PM PST 23 |
Dec 24 12:41:27 PM PST 23 |
59637200 ps |
| T293 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.1936832860 |
|
|
Dec 24 12:40:11 PM PST 23 |
Dec 24 12:41:02 PM PST 23 |
6202255500 ps |
| T1165 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2395363321 |
|
|
Dec 24 12:40:36 PM PST 23 |
Dec 24 12:40:54 PM PST 23 |
88478600 ps |
| T229 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.750766057 |
|
|
Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:33 PM PST 23 |
108938300 ps |
| T1166 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.434464816 |
|
|
Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:29 PM PST 23 |
44411600 ps |
| T301 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.470534484 |
|
|
Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:31 PM PST 23 |
61278300 ps |
| T231 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.439407932 |
|
|
Dec 24 12:40:50 PM PST 23 |
Dec 24 12:41:07 PM PST 23 |
28587800 ps |
| T1167 |
/workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.2984478295 |
|
|
Dec 24 12:41:37 PM PST 23 |
Dec 24 12:41:58 PM PST 23 |
17863300 ps |
| T232 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4104771479 |
|
|
Dec 24 12:41:10 PM PST 23 |
Dec 24 12:47:35 PM PST 23 |
336445400 ps |
| T294 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3948059226 |
|
|
Dec 24 12:40:48 PM PST 23 |
Dec 24 12:41:08 PM PST 23 |
116462300 ps |
| T297 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3286917290 |
|
|
Dec 24 12:40:14 PM PST 23 |
Dec 24 12:40:55 PM PST 23 |
1184846600 ps |
| T298 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.988927867 |
|
|
Dec 24 12:41:17 PM PST 23 |
Dec 24 12:41:35 PM PST 23 |
60385900 ps |
| T258 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1305768608 |
|
|
Dec 24 12:41:15 PM PST 23 |
Dec 24 12:41:34 PM PST 23 |
46507000 ps |
| T1168 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.7212724 |
|
|
Dec 24 12:40:14 PM PST 23 |
Dec 24 12:40:31 PM PST 23 |
13285700 ps |
| T312 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.3791243167 |
|
|
Dec 24 12:41:12 PM PST 23 |
Dec 24 12:56:02 PM PST 23 |
732329400 ps |
| T1169 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1395959315 |
|
|
Dec 24 12:40:36 PM PST 23 |
Dec 24 12:40:56 PM PST 23 |
77107700 ps |
| T1170 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_rw.3121454485 |
|
|
Dec 24 12:42:08 PM PST 23 |
Dec 24 12:42:27 PM PST 23 |
35891300 ps |
| T295 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2960641543 |
|
|
Dec 24 12:40:43 PM PST 23 |
Dec 24 12:41:24 PM PST 23 |
2935550800 ps |
| T257 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_errors.345217424 |
|
|
Dec 24 12:40:39 PM PST 23 |
Dec 24 12:40:57 PM PST 23 |
135370400 ps |
| T1171 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2519207634 |
|
|
Dec 24 12:41:34 PM PST 23 |
Dec 24 12:41:54 PM PST 23 |
15511000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1061482059 |
|
|
Dec 24 12:41:11 PM PST 23 |
Dec 24 12:41:25 PM PST 23 |
14763700 ps |
| T1173 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2377761689 |
|
|
Dec 24 12:40:34 PM PST 23 |
Dec 24 12:40:48 PM PST 23 |
16975200 ps |
| T1174 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1646019687 |
|
|
Dec 24 12:41:13 PM PST 23 |
Dec 24 12:41:29 PM PST 23 |
30105400 ps |
| T316 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3560257569 |
|
|
Dec 24 12:40:50 PM PST 23 |
Dec 24 12:48:36 PM PST 23 |
4991495500 ps |
| T259 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.701052408 |
|
|
Dec 24 12:40:11 PM PST 23 |
Dec 24 12:40:30 PM PST 23 |
583182500 ps |
| T1175 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2955548467 |
|
|
Dec 24 12:41:36 PM PST 23 |
Dec 24 12:42:00 PM PST 23 |
33617000 ps |
| T1176 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3558146648 |
|
|
Dec 24 12:40:38 PM PST 23 |
Dec 24 12:40:55 PM PST 23 |
13431000 ps |
| T319 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1213752112 |
|
|
Dec 24 12:41:13 PM PST 23 |
Dec 24 12:48:56 PM PST 23 |
3865694600 ps |
| T243 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.381667682 |
|
|
Dec 24 12:40:09 PM PST 23 |
Dec 24 12:40:24 PM PST 23 |
18085000 ps |
| T1177 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_rw.4109098864 |
|
|
Dec 24 12:40:15 PM PST 23 |
Dec 24 12:40:33 PM PST 23 |
31068500 ps |
| T1178 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.539429285 |
|
|
Dec 24 12:41:34 PM PST 23 |
Dec 24 12:41:55 PM PST 23 |
156566800 ps |
| T1179 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3972007347 |
|
|
Dec 24 12:41:37 PM PST 23 |
Dec 24 12:42:01 PM PST 23 |
226547400 ps |
| T1180 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.4123719208 |
|
|
Dec 24 12:40:12 PM PST 23 |
Dec 24 12:41:00 PM PST 23 |
44315000 ps |
| T263 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3361316220 |
|
|
Dec 24 12:41:13 PM PST 23 |
Dec 24 12:41:30 PM PST 23 |
41441500 ps |
| T1181 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3119720138 |
|
|
Dec 24 12:40:50 PM PST 23 |
Dec 24 12:41:10 PM PST 23 |
53868600 ps |
| T1182 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.761156777 |
|
|
Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:26 PM PST 23 |
30773900 ps |
| T1183 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3069991250 |
|
|
Dec 24 12:39:43 PM PST 23 |
Dec 24 12:40:01 PM PST 23 |
23365000 ps |
| T1184 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2339542727 |
|
|
Dec 24 12:40:47 PM PST 23 |
Dec 24 12:41:03 PM PST 23 |
49306500 ps |
| T1185 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3243126112 |
|
|
Dec 24 12:41:37 PM PST 23 |
Dec 24 12:41:58 PM PST 23 |
148790700 ps |
| T262 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.3217385861 |
|
|
Dec 24 12:40:11 PM PST 23 |
Dec 24 12:40:29 PM PST 23 |
41009500 ps |
| T1186 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.3198451639 |
|
|
Dec 24 12:40:48 PM PST 23 |
Dec 24 12:41:03 PM PST 23 |
23024900 ps |
| T317 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.4273821976 |
|
|
Dec 24 12:40:49 PM PST 23 |
Dec 24 12:48:31 PM PST 23 |
248205500 ps |
| T1187 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2196204949 |
|
|
Dec 24 12:41:34 PM PST 23 |
Dec 24 12:41:54 PM PST 23 |
32235300 ps |
| T261 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3734279795 |
|
|
Dec 24 12:40:36 PM PST 23 |
Dec 24 12:48:11 PM PST 23 |
373127900 ps |
| T299 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3442801485 |
|
|
Dec 24 12:40:22 PM PST 23 |
Dec 24 12:40:58 PM PST 23 |
222145600 ps |
| T1188 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1136858251 |
|
|
Dec 24 12:40:09 PM PST 23 |
Dec 24 12:40:24 PM PST 23 |
18163100 ps |
| T264 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.2901746825 |
|
|
Dec 24 12:42:36 PM PST 23 |
Dec 24 12:42:58 PM PST 23 |
73736000 ps |
| T244 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.498525444 |
|
|
Dec 24 12:40:08 PM PST 23 |
Dec 24 12:40:23 PM PST 23 |
80688600 ps |
| T1189 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.2325477005 |
|
|
Dec 24 12:40:43 PM PST 23 |
Dec 24 12:40:59 PM PST 23 |
86071300 ps |
| T1190 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2976879819 |
|
|
Dec 24 12:41:34 PM PST 23 |
Dec 24 12:41:55 PM PST 23 |
30281500 ps |
| T1191 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3684676314 |
|
|
Dec 24 12:40:49 PM PST 23 |
Dec 24 12:41:03 PM PST 23 |
14712300 ps |
| T1192 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3596136031 |
|
|
Dec 24 12:41:13 PM PST 23 |
Dec 24 12:41:32 PM PST 23 |
28082900 ps |
| T267 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.891051294 |
|
|
Dec 24 12:41:16 PM PST 23 |
Dec 24 12:41:33 PM PST 23 |
102760600 ps |
| T245 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.81101051 |
|
|
Dec 24 12:40:08 PM PST 23 |
Dec 24 12:40:23 PM PST 23 |
32643600 ps |
| T1193 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3895059280 |
|
|
Dec 24 12:41:34 PM PST 23 |
Dec 24 12:41:55 PM PST 23 |
28267500 ps |
| T1194 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.962234630 |
|
|
Dec 24 12:41:38 PM PST 23 |
Dec 24 12:41:57 PM PST 23 |
52924300 ps |
| T1195 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1106538501 |
|
|
Dec 24 12:41:35 PM PST 23 |
Dec 24 12:41:57 PM PST 23 |
181630500 ps |
| T1196 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.494955027 |
|
|
Dec 24 12:41:11 PM PST 23 |
Dec 24 12:41:28 PM PST 23 |
50799000 ps |
| T1197 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.1485790288 |
|
|
Dec 24 12:40:37 PM PST 23 |
Dec 24 12:40:52 PM PST 23 |
17781800 ps |
| T1198 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3981320568 |
|
|
Dec 24 12:40:09 PM PST 23 |
Dec 24 12:40:24 PM PST 23 |
24260000 ps |
| T260 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2307692812 |
|
|
Dec 24 12:40:47 PM PST 23 |
Dec 24 12:41:06 PM PST 23 |
255319200 ps |
| T1199 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.4136866443 |
|
|
Dec 24 12:40:09 PM PST 23 |
Dec 24 12:40:47 PM PST 23 |
331069300 ps |
| T1200 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2672306097 |
|
|
Dec 24 12:41:11 PM PST 23 |
Dec 24 12:41:25 PM PST 23 |
20545000 ps |
| T1201 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.744455292 |
|
|
Dec 24 12:41:09 PM PST 23 |
Dec 24 12:41:26 PM PST 23 |
98912700 ps |
| T313 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3065419240 |
|
|
Dec 24 12:40:10 PM PST 23 |
Dec 24 12:55:20 PM PST 23 |
952561500 ps |
| T1202 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1389425795 |
|
|
Dec 24 12:40:45 PM PST 23 |
Dec 24 12:41:01 PM PST 23 |
26930700 ps |
| T1203 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1024950441 |
|
|
Dec 24 12:40:47 PM PST 23 |
Dec 24 12:41:05 PM PST 23 |
291348100 ps |
| T1204 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1989205183 |
|
|
Dec 24 12:40:34 PM PST 23 |
Dec 24 12:41:19 PM PST 23 |
1514795200 ps |
| T1205 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3967320725 |
|
|
Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:26 PM PST 23 |
27378700 ps |
| T1206 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.1389858737 |
|
|
Dec 24 12:41:13 PM PST 23 |
Dec 24 12:41:28 PM PST 23 |
14445400 ps |
| T265 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2364114303 |
|
|
Dec 24 12:40:12 PM PST 23 |
Dec 24 12:40:33 PM PST 23 |
119936700 ps |
| T1207 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3546046251 |
|
|
Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:47 PM PST 23 |
125576300 ps |
| T1208 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1622673057 |
|
|
Dec 24 12:41:35 PM PST 23 |
Dec 24 12:41:58 PM PST 23 |
21000100 ps |
| T315 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2599323541 |
|
|
Dec 24 12:40:35 PM PST 23 |
Dec 24 12:48:15 PM PST 23 |
380777000 ps |
| T1209 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.962745869 |
|
|
Dec 24 12:39:38 PM PST 23 |
Dec 24 12:39:57 PM PST 23 |
19957400 ps |
| T320 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1488532007 |
|
|
Dec 24 12:41:09 PM PST 23 |
Dec 24 12:56:08 PM PST 23 |
811233700 ps |
| T1210 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.3353847249 |
|
|
Dec 24 12:40:15 PM PST 23 |
Dec 24 12:40:29 PM PST 23 |
35225400 ps |
| T246 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1690402697 |
|
|
Dec 24 12:40:35 PM PST 23 |
Dec 24 12:40:50 PM PST 23 |
47271400 ps |
| T1211 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1355782017 |
|
|
Dec 24 12:41:10 PM PST 23 |
Dec 24 12:41:27 PM PST 23 |
66535800 ps |
| T1212 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.1379751363 |
|
|
Dec 24 12:40:34 PM PST 23 |
Dec 24 12:40:52 PM PST 23 |
148552300 ps |
| T1213 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1362852070 |
|
|
Dec 24 12:40:36 PM PST 23 |
Dec 24 12:41:04 PM PST 23 |
62774700 ps |
| T1214 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.369547134 |
|
|
Dec 24 12:40:35 PM PST 23 |
Dec 24 12:40:54 PM PST 23 |
492061300 ps |
| T1215 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2865591928 |
|
|
Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:29 PM PST 23 |
11742300 ps |
| T1216 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2451921587 |
|
|
Dec 24 12:40:15 PM PST 23 |
Dec 24 12:40:56 PM PST 23 |
501979300 ps |
| T321 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2780966055 |
|
|
Dec 24 12:41:13 PM PST 23 |
Dec 24 12:53:59 PM PST 23 |
733930400 ps |
| T314 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2179351093 |
|
|
Dec 24 12:41:10 PM PST 23 |
Dec 24 12:56:11 PM PST 23 |
1634878000 ps |
| T1217 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.214907916 |
|
|
Dec 24 12:40:36 PM PST 23 |
Dec 24 12:40:54 PM PST 23 |
33239000 ps |
| T1218 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2613481138 |
|
|
Dec 24 12:40:46 PM PST 23 |
Dec 24 12:41:02 PM PST 23 |
13272500 ps |
| T266 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2161173527 |
|
|
Dec 24 12:40:34 PM PST 23 |
Dec 24 12:40:53 PM PST 23 |
202007100 ps |
| T1219 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.201819141 |
|
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Dec 24 12:40:12 PM PST 23 |
Dec 24 12:55:04 PM PST 23 |
687015800 ps |
| T1220 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.2692437948 |
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Dec 24 12:40:37 PM PST 23 |
Dec 24 12:40:57 PM PST 23 |
30049300 ps |
| T1221 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.2973559671 |
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Dec 24 12:41:10 PM PST 23 |
Dec 24 12:41:24 PM PST 23 |
61613600 ps |
| T1222 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.420184567 |
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Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:28 PM PST 23 |
532566600 ps |
| T1223 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.967528965 |
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Dec 24 12:41:34 PM PST 23 |
Dec 24 12:41:55 PM PST 23 |
15236800 ps |
| T1224 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3541477145 |
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Dec 24 12:40:48 PM PST 23 |
Dec 24 12:41:03 PM PST 23 |
50261500 ps |
| T1225 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.260970265 |
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Dec 24 12:41:17 PM PST 23 |
Dec 24 12:41:32 PM PST 23 |
17118400 ps |
| T318 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.219172196 |
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Dec 24 12:42:09 PM PST 23 |
Dec 24 12:57:13 PM PST 23 |
1041638900 ps |
| T1226 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3397822900 |
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Dec 24 12:41:13 PM PST 23 |
Dec 24 12:41:32 PM PST 23 |
136712600 ps |
| T1227 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.338877797 |
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Dec 24 12:40:47 PM PST 23 |
Dec 24 12:41:02 PM PST 23 |
20372700 ps |
| T1228 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.70185009 |
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Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:29 PM PST 23 |
83008000 ps |
| T1229 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.484715383 |
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Dec 24 12:41:11 PM PST 23 |
Dec 24 12:41:26 PM PST 23 |
42590200 ps |
| T1230 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.1426376402 |
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Dec 24 12:41:37 PM PST 23 |
Dec 24 12:41:58 PM PST 23 |
24841700 ps |
| T1231 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3713607232 |
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Dec 24 12:41:12 PM PST 23 |
Dec 24 12:41:32 PM PST 23 |
341396400 ps |
| T1232 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1296387288 |
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Dec 24 12:40:45 PM PST 23 |
Dec 24 12:41:05 PM PST 23 |
334003000 ps |
| T1233 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4166037618 |
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Dec 24 12:41:10 PM PST 23 |
Dec 24 12:41:27 PM PST 23 |
36398300 ps |
| T1234 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.480151365 |
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Dec 24 12:39:43 PM PST 23 |
Dec 24 12:39:59 PM PST 23 |
66265300 ps |
| T1235 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3984606605 |
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Dec 24 12:41:10 PM PST 23 |
Dec 24 12:41:24 PM PST 23 |
18459600 ps |
| T1236 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.1499048725 |
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Dec 24 12:41:14 PM PST 23 |
Dec 24 12:41:32 PM PST 23 |
75856500 ps |
| T1237 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.981431723 |
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Dec 24 12:41:35 PM PST 23 |
Dec 24 12:41:57 PM PST 23 |
30704900 ps |
| T1238 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2543433923 |
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Dec 24 12:40:46 PM PST 23 |
Dec 24 12:41:03 PM PST 23 |
27580200 ps |
| T1239 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2116601375 |
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Dec 24 12:40:36 PM PST 23 |
Dec 24 12:40:53 PM PST 23 |
90683200 ps |
| T1240 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.3697513580 |
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Dec 24 12:40:47 PM PST 23 |
Dec 24 12:41:01 PM PST 23 |
14901500 ps |
| T1241 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3413987770 |
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Dec 24 12:40:48 PM PST 23 |
Dec 24 12:41:08 PM PST 23 |
30679400 ps |
| T300 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2672627101 |
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Dec 24 12:40:14 PM PST 23 |
Dec 24 12:40:53 PM PST 23 |
793889900 ps |
| T1242 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3237141675 |
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Dec 24 12:40:35 PM PST 23 |
Dec 24 12:40:50 PM PST 23 |
200177500 ps |
| T1243 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.77789489 |
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Dec 24 12:40:47 PM PST 23 |
Dec 24 12:41:02 PM PST 23 |
18158500 ps |
| T1244 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3109436179 |
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Dec 24 12:41:33 PM PST 23 |
Dec 24 12:41:54 PM PST 23 |
17390500 ps |
| T1245 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3705354575 |
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Dec 24 12:41:16 PM PST 23 |
Dec 24 12:41:30 PM PST 23 |
15008000 ps |
| T1246 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.358584635 |
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Dec 24 12:40:37 PM PST 23 |
Dec 24 12:40:54 PM PST 23 |
43481200 ps |
| T1247 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2015810546 |
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Dec 24 12:41:37 PM PST 23 |
Dec 24 12:42:00 PM PST 23 |
27073900 ps |
| T1248 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.684547869 |
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Dec 24 12:41:35 PM PST 23 |
Dec 24 12:41:58 PM PST 23 |
25351200 ps |
| T1249 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1423401791 |
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Dec 24 12:40:09 PM PST 23 |
Dec 24 12:40:26 PM PST 23 |
17977100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1628226926 |
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Dec 24 12:40:10 PM PST 23 |
Dec 24 12:40:28 PM PST 23 |
67274400 ps |
| T1251 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.2393722757 |
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Dec 24 12:40:09 PM PST 23 |
Dec 24 12:40:24 PM PST 23 |
16112400 ps |