FLASH_CTRL Simulation Results

Sunday December 24 2023 20:02:26 UTC

GitHub Revision: `671f2b57e2`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96716765175854174075659971574604807242747408006700796360560480210023744343645

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.664m	54.829us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.910s	18.354us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.460s	44.315us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.830s	492.061us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.403m	5.008ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.042m	1.241ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.990s	160.304us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.830s	492.061us	20	20	100.00
		flash_ctrl_csr_aliasing	1.042m	1.241ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.630s	28.236us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.560s	80.689us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.590s	35.851us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.517m	58.627us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	38.438m	1.590s	3	3	100.00
		flash_ctrl_hw_rma_reset	15.542m	160.175ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.110s	118.977us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	36.044m	279.420ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.286m	4.158ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.927m	7.648ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	56.844m	203.462ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.217m	2.774ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.640s	104.153us	39	40	97.50
		flash_ctrl_rw_evict_all_en	38.180s	201.961us	38	40	95.00
		flash_ctrl_re_evict	39.230s	125.440us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.590m	2.128ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.590m	2.128ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	9.057m	6.997ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.240s	1.668ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	25.822m	788.800us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.469m	15.330ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.227m	471.375us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	45.272m	3.361ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.640s	77.844us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	2.797m	959.485us	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	36.693m	120.021ms	46	50	92.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.340s	16.850us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	22.025m	1.075ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.844m	57.512ms	50	50	100.00
		flash_ctrl_otp_reset	2.265m	41.761us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	38.438m	1.590s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.163m	1.169ms	40	40	100.00
		flash_ctrl_intr_wr	2.196m	21.688ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.953m	102.205ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	10.258m	227.211ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.541m	4.020ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.264m	2.791ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.930s	62.974us	5	5	100.00
		flash_ctrl_ro_derr	2.594m	2.239ms	10	10	100.00
		flash_ctrl_rw_derr	10.873m	38.398ms	10	10	100.00
		flash_ctrl_derr_detect	1.751m	294.237us	5	5	100.00
		flash_ctrl_integrity	11.574m	17.088ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.040s	24.230us	5	5	100.00
		flash_ctrl_ro_serr	2.380m	816.706us	10	10	100.00
		flash_ctrl_rw_serr	11.556m	43.914ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.234m	1.249ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.884m	4.353ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.587m	4.136ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.630s	211.897us	1	1	100.00
		flash_ctrl_read_word_sweep	13.900s	25.727us	1	1	100.00
		flash_ctrl_ro	2.068m	598.182us	20	20	100.00
		flash_ctrl_rw	10.518m	7.712ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	42.050s	342.197us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.948m	100.511ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.949m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.320s	70.454us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.060s	30.105us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.550s	119.937us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.550s	119.937us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.460s	44.315us	5	5	100.00
		flash_ctrl_csr_rw	17.830s	492.061us	20	20	100.00
		flash_ctrl_csr_aliasing	1.042m	1.241ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.300s	222.146us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.460s	44.315us	5	5	100.00
		flash_ctrl_csr_rw	17.830s	492.061us	20	20	100.00
		flash_ctrl_csr_aliasing	1.042m	1.241ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.300s	222.146us	20	20	100.00
V2		TOTAL			1005	1013	99.21
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.440s	13.286us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.440s	13.286us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.440s	13.286us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.440s	13.286us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.100s	27.074us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.306h	1.589ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.137m	859.349us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.137m	859.349us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.137m	859.349us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.160s	64.422us	3	3	100.00
		flash_ctrl_wr_intg	15.370s	770.534us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.664m	54.829us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.265m	41.761us	80	80	100.00
		flash_ctrl_disable	36.693m	120.021ms	46	50	92.00
		flash_ctrl_sec_info_access	1.409m	11.668ms	50	50	100.00
		flash_ctrl_connect	16.340s	16.850us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.940s	51.965us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.830s	492.061us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.440s	13.286us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.830s	492.061us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.440s	13.286us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.830s	492.061us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.440s	13.286us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	36.693m	120.021ms	46	50	92.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.160s	64.422us	3	3	100.00
		flash_ctrl_access_after_disable	14.120s	111.358us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	36.693m	120.021ms	46	50	92.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.240s	1.668ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.518m	7.712ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.556m	43.914ms	10	10	100.00
		flash_ctrl_rw_derr	10.873m	38.398ms	10	10	100.00
		flash_ctrl_integrity	11.574m	17.088ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	38.438m	1.590s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.306h	1.589ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.306h	1.589ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.306h	1.589ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.306h	1.589ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.660s	114.638us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.310s	15.502us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.430s	16.853us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.306h	1.589ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.306h	1.589ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.306h	1.589ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.860s	86.455us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1270	1278	99.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	51	92.73
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.74	95.88	94.38	98.95	92.52	98.57	98.30	98.62

Failure Buckets

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 10.flash_ctrl_rw_evict_all_en.28191525271839733436995488436311952837830859258898769727526451989389995199984
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 43425.1 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 43425.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.flash_ctrl_rw_evict_all_en.88754861511937235153073183009447519483925411126198403240947674155952708129891
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 113540.3 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 113540.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_rw_evict has 1 failures.
  - 36.flash_ctrl_rw_evict.9054800178563152876258159157753317611967793264449582750611627986435774880911
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 14750.8 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 14750.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@80295) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

0.flash_ctrl_disable.41910674633057032623014600356732060830083877813660341827981971401075677778362
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 11536.7 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@80295) { a_addr: 'hf1d721b0  a_data: 'he5b5256d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h79  a_opcode: 'h0  a_user: 'h243c5  d_param: 'h0  d_source: 'h79  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 11536.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 1.flash_ctrl_full_mem_access.67035559270369950820702363039017489136719588602099046830572921590807645463084
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:55886b5f-10b0-4f6d-9dca-ef78853d64e7
```
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=*) == * has 1 failures:
- Test flash_ctrl_disable has 1 failures.
  - 24.flash_ctrl_disable.85069655660128309919821304946440865771634904774069213576930616498408756238297
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 10014775.7 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=0x46995774) == 0x1
  UVM_INFO @ 10014775.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@79521) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

42.flash_ctrl_disable.90270868285524600906269417968816236157690665619638845696411828703738863594067
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 5218.0 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@79521) { a_addr: 'h3e704bb0  a_data: 'hd476fae5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hc2  a_opcode: 'h0  a_user: 'h265a0  d_param: 'h0  d_source: 'hc2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5218.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=*) == * has 1 failures:
- Test flash_ctrl_disable has 1 failures.
  - 49.flash_ctrl_disable.93634046813727140024009923151470443007321263150560199577030591771507028730575
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 120020794.6 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=0x3fc75f70) == 0x1
  UVM_INFO @ 120020794.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```