Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	342675	1		T54	5		T61	5		T147	5
all_values[1]	342675	1		T54	5		T61	5		T147	5
all_values[2]	342675	1		T54	5		T61	5		T147	5
all_values[3]	342675	1		T54	5		T61	5		T147	5
all_values[4]	342675	1		T54	5		T61	5		T147	5
all_values[5]	342675	1		T54	5		T61	5		T147	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10253	1		T54	12		T61	11		T147	15
auto[1]	2045797	1		T54	18		T61	19		T147	15

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1665570	1		T54	11		T61	20		T147	24
auto[1]	390480	1		T54	19		T61	10		T147	6

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1248	1		T54	1		T61	1		T139	1
all_values[0]	auto[0]	auto[1]	431	1		T54	3		T147	1		T193	4
all_values[0]	auto[1]	auto[0]	281053	1		T61	2		T147	3		T193	2
all_values[0]	auto[1]	auto[1]	59943	1		T54	1		T61	2		T147	1
all_values[1]	auto[0]	auto[0]	1659	1		T147	3		T139	1		T140	1
all_values[1]	auto[0]	auto[1]	58	1		T61	1		T193	3		T315	1
all_values[1]	auto[1]	auto[0]	265411	1		T54	1		T61	4		T147	2
all_values[1]	auto[1]	auto[1]	75547	1		T54	4		T315	2		T296	1
all_values[2]	auto[0]	auto[0]	1585	1		T54	1		T61	1		T139	1
all_values[2]	auto[0]	auto[1]	132	1		T54	2		T147	1		T193	1
all_values[2]	auto[1]	auto[0]	330328	1		T54	1		T61	3		T147	4
all_values[2]	auto[1]	auto[1]	10630	1		T54	1		T61	1		T193	1
all_values[3]	auto[0]	auto[0]	1568	1		T54	1		T61	2		T147	5
all_values[3]	auto[0]	auto[1]	123	1		T61	2		T239	1		T316	3
all_values[3]	auto[1]	auto[0]	197714	1		T54	2		T61	1		T193	4
all_values[3]	auto[1]	auto[1]	143270	1		T54	2		T193	3		T296	3
all_values[4]	auto[0]	auto[0]	1198	1		T54	1		T61	3		T147	4
all_values[4]	auto[0]	auto[1]	542	1		T54	2		T61	1		T193	1
all_values[4]	auto[1]	auto[0]	241354	1		T54	2		T147	1		T193	3
all_values[4]	auto[1]	auto[1]	99581	1		T61	1		T193	1		T315	2
all_values[5]	auto[0]	auto[0]	1560	1		T139	1		T140	1		T141	1
all_values[5]	auto[0]	auto[1]	149	1		T54	1		T147	1		T193	3
all_values[5]	auto[1]	auto[0]	340892	1		T54	1		T61	3		T147	2
all_values[5]	auto[1]	auto[1]	74	1		T54	3		T61	2		T147	2