Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T23 |
2 |
|
T25 |
10 |
|
T46 |
10 |
| others[1] |
246 |
1 |
|
T23 |
2 |
|
T25 |
12 |
|
T46 |
11 |
| others[2] |
184 |
1 |
|
T8 |
1 |
|
T25 |
7 |
|
T46 |
8 |
| others[3] |
366 |
1 |
|
T23 |
1 |
|
T25 |
17 |
|
T46 |
8 |
| false |
122 |
1 |
|
T27 |
1 |
|
T25 |
4 |
|
T46 |
8 |
| true |
12156 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T1 |
1 |
|
T25 |
7 |
|
T46 |
10 |
| others[1] |
246 |
1 |
|
T23 |
3 |
|
T8 |
1 |
|
T25 |
17 |
| others[2] |
236 |
1 |
|
T27 |
1 |
|
T25 |
10 |
|
T46 |
12 |
| others[3] |
383 |
1 |
|
T23 |
2 |
|
T25 |
13 |
|
T46 |
15 |
| false |
92 |
1 |
|
T25 |
4 |
|
T46 |
6 |
|
T127 |
3 |
| true |
12156 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7700 |
1 |
|
T140 |
1 |
|
T297 |
1 |
|
T317 |
1 |
| others[1] |
1242 |
1 |
|
T147 |
1 |
|
T143 |
1 |
|
T239 |
1 |
| others[2] |
1218 |
1 |
|
T146 |
1 |
|
T149 |
1 |
|
T341 |
1 |
| others[3] |
2099 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T141 |
1 |
| false |
609 |
1 |
|
T139 |
1 |
|
T144 |
1 |
|
T241 |
1 |
| true |
441 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7693 |
1 |
|
T142 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| others[1] |
1258 |
1 |
|
T315 |
1 |
|
T241 |
1 |
|
T349 |
1 |
| others[2] |
1233 |
1 |
|
T61 |
1 |
|
T141 |
1 |
|
T297 |
1 |
| others[3] |
2067 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| false |
654 |
1 |
|
T54 |
1 |
|
T144 |
1 |
|
T146 |
1 |
| true |
404 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
1 |
| others[1] |
110 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
2 |
| others[2] |
116 |
1 |
|
T23 |
2 |
|
T25 |
6 |
|
T46 |
4 |
| others[3] |
179 |
1 |
|
T23 |
1 |
|
T25 |
6 |
|
T46 |
6 |
| false |
52 |
1 |
|
T23 |
1 |
|
T25 |
3 |
|
T46 |
1 |
| true |
12737 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T25 |
9 |
|
T46 |
13 |
|
T351 |
1 |
| others[1] |
227 |
1 |
|
T23 |
2 |
|
T25 |
6 |
|
T46 |
12 |
| others[2] |
236 |
1 |
|
T27 |
1 |
|
T25 |
7 |
|
T46 |
13 |
| others[3] |
405 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T25 |
15 |
| false |
108 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
4 |
| true |
12104 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7535 |
1 |
|
T315 |
1 |
|
T5 |
131 |
|
T13 |
3 |
| others[1] |
1066 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T143 |
1 |
| others[2] |
1056 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| others[3] |
1722 |
1 |
|
T142 |
1 |
|
T193 |
1 |
|
T296 |
1 |
| false |
528 |
1 |
|
T61 |
1 |
|
T316 |
1 |
|
T341 |
1 |
| true |
1402 |
1 |
|
T49 |
1 |
|
T53 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T23 |
2 |
|
T27 |
1 |
|
T25 |
8 |
| others[1] |
218 |
1 |
|
T1 |
1 |
|
T25 |
8 |
|
T46 |
10 |
| others[2] |
217 |
1 |
|
T25 |
11 |
|
T46 |
11 |
|
T39 |
1 |
| others[3] |
430 |
1 |
|
T23 |
2 |
|
T25 |
23 |
|
T46 |
14 |
| false |
133 |
1 |
|
T25 |
4 |
|
T46 |
12 |
|
T48 |
1 |
| true |
12077 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T25 |
7 |
|
T46 |
5 |
|
T65 |
1 |
| others[1] |
215 |
1 |
|
T1 |
1 |
|
T25 |
13 |
|
T46 |
11 |
| others[2] |
242 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T25 |
12 |
| others[3] |
379 |
1 |
|
T27 |
1 |
|
T25 |
14 |
|
T46 |
20 |
| false |
119 |
1 |
|
T25 |
7 |
|
T46 |
4 |
|
T41 |
1 |
| true |
12128 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7658 |
1 |
|
T54 |
1 |
|
T145 |
1 |
|
T149 |
1 |
| others[1] |
1232 |
1 |
|
T142 |
1 |
|
T143 |
1 |
|
T315 |
1 |
| others[2] |
1190 |
1 |
|
T139 |
1 |
|
T150 |
1 |
|
T343 |
1 |
| others[3] |
2152 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T140 |
1 |
| false |
642 |
1 |
|
T349 |
1 |
|
T341 |
1 |
|
T345 |
1 |
| true |
435 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T147 |
1 |
|
T144 |
1 |
|
T296 |
1 |
| others[1] |
1206 |
1 |
|
T61 |
1 |
|
T317 |
1 |
|
T265 |
1 |
| others[2] |
1295 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T141 |
1 |
| others[3] |
2073 |
1 |
|
T140 |
1 |
|
T315 |
1 |
|
T297 |
1 |
| false |
618 |
1 |
|
T193 |
1 |
|
T341 |
1 |
|
T6 |
3 |
| true |
415 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T25 |
4 |
|
T46 |
5 |
|
T352 |
1 |
| others[1] |
101 |
1 |
|
T23 |
5 |
|
T25 |
3 |
|
T46 |
2 |
| others[2] |
112 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T46 |
2 |
| others[3] |
175 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
7 |
| false |
43 |
1 |
|
T25 |
2 |
|
T46 |
1 |
|
T342 |
1 |
| true |
6333 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T23 |
2 |
|
T25 |
9 |
|
T46 |
6 |
| others[1] |
236 |
1 |
|
T25 |
8 |
|
T46 |
10 |
|
T121 |
1 |
| others[2] |
253 |
1 |
|
T25 |
7 |
|
T46 |
14 |
|
T39 |
1 |
| others[3] |
390 |
1 |
|
T23 |
3 |
|
T25 |
17 |
|
T46 |
11 |
| false |
136 |
1 |
|
T23 |
1 |
|
T25 |
8 |
|
T46 |
1 |
| true |
5628 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T143 |
1 |
| others[1] |
1067 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T140 |
1 |
| others[2] |
1074 |
1 |
|
T144 |
1 |
|
T347 |
1 |
|
T20 |
1 |
| others[3] |
1704 |
1 |
|
T147 |
1 |
|
T239 |
1 |
|
T265 |
1 |
| false |
583 |
1 |
|
T241 |
1 |
|
T150 |
1 |
|
T346 |
1 |
| true |
1371 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T45 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T25 |
8 |
|
T46 |
7 |
|
T123 |
1 |
| others[1] |
216 |
1 |
|
T23 |
1 |
|
T25 |
7 |
|
T46 |
8 |
| others[2] |
228 |
1 |
|
T1 |
1 |
|
T25 |
10 |
|
T46 |
6 |
| others[3] |
413 |
1 |
|
T23 |
4 |
|
T8 |
1 |
|
T25 |
11 |
| false |
118 |
1 |
|
T25 |
7 |
|
T46 |
2 |
|
T127 |
1 |
| true |
5654 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T25 |
14 |
|
T46 |
13 |
|
T65 |
1 |
| others[1] |
229 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T25 |
9 |
| others[2] |
244 |
1 |
|
T23 |
2 |
|
T25 |
12 |
|
T46 |
10 |
| others[3] |
370 |
1 |
|
T23 |
1 |
|
T27 |
1 |
|
T25 |
11 |
| false |
94 |
1 |
|
T25 |
5 |
|
T46 |
6 |
|
T127 |
2 |
| true |
5704 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1209 |
1 |
|
T143 |
1 |
|
T241 |
1 |
|
T244 |
1 |
| others[1] |
1262 |
1 |
|
T193 |
1 |
|
T297 |
1 |
|
T265 |
1 |
| others[2] |
1243 |
1 |
|
T147 |
1 |
|
T142 |
1 |
|
T146 |
1 |
| others[3] |
2057 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T139 |
1 |
| false |
667 |
1 |
|
T315 |
1 |
|
T144 |
1 |
|
T296 |
1 |
| true |
431 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T193 |
1 |
|
T315 |
1 |
|
T344 |
1 |
| others[1] |
1242 |
1 |
|
T147 |
1 |
|
T142 |
1 |
|
T143 |
1 |
| others[2] |
1315 |
1 |
|
T54 |
1 |
|
T296 |
1 |
|
T239 |
1 |
| others[3] |
2051 |
1 |
|
T61 |
1 |
|
T141 |
1 |
|
T145 |
1 |
| false |
613 |
1 |
|
T139 |
1 |
|
T140 |
1 |
|
T345 |
1 |
| true |
414 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T23 |
2 |
|
T25 |
7 |
|
T46 |
7 |
| others[1] |
106 |
1 |
|
T23 |
3 |
|
T25 |
6 |
|
T46 |
3 |
| others[2] |
92 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
4 |
| others[3] |
204 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
6 |
| false |
56 |
1 |
|
T23 |
1 |
|
T25 |
2 |
|
T46 |
1 |
| true |
6310 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T23 |
2 |
|
T25 |
11 |
|
T46 |
10 |
| others[1] |
239 |
1 |
|
T25 |
11 |
|
T46 |
11 |
|
T351 |
1 |
| others[2] |
244 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T25 |
9 |
| others[3] |
388 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
16 |
| false |
129 |
1 |
|
T25 |
6 |
|
T46 |
5 |
|
T40 |
3 |
| true |
5647 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T142 |
1 |
|
T146 |
1 |
|
T149 |
1 |
| others[1] |
1101 |
1 |
|
T54 |
1 |
|
T315 |
1 |
|
T317 |
1 |
| others[2] |
1091 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T140 |
1 |
| others[3] |
1760 |
1 |
|
T297 |
1 |
|
T145 |
1 |
|
T349 |
1 |
| false |
523 |
1 |
|
T139 |
1 |
|
T193 |
1 |
|
T296 |
1 |
| true |
1328 |
1 |
|
T8 |
1 |
|
T53 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
8 |
| others[1] |
235 |
1 |
|
T23 |
1 |
|
T25 |
8 |
|
T46 |
12 |
| others[2] |
223 |
1 |
|
T23 |
2 |
|
T25 |
6 |
|
T46 |
7 |
| others[3] |
390 |
1 |
|
T25 |
14 |
|
T46 |
18 |
|
T76 |
1 |
| false |
113 |
1 |
|
T25 |
3 |
|
T46 |
4 |
|
T65 |
1 |
| true |
5684 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T23 |
1 |
|
T25 |
10 |
|
T46 |
10 |
| others[1] |
222 |
1 |
|
T25 |
11 |
|
T46 |
11 |
|
T348 |
1 |
| others[2] |
236 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
8 |
| others[3] |
349 |
1 |
|
T23 |
3 |
|
T25 |
21 |
|
T46 |
19 |
| false |
102 |
1 |
|
T25 |
4 |
|
T46 |
4 |
|
T127 |
6 |
| true |
5730 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T139 |
1 |
| others[1] |
1225 |
1 |
|
T144 |
1 |
|
T296 |
1 |
|
T145 |
1 |
| others[2] |
1248 |
1 |
|
T54 |
1 |
|
T142 |
1 |
|
T149 |
1 |
| others[3] |
2090 |
1 |
|
T140 |
1 |
|
T143 |
1 |
|
T315 |
1 |
| false |
622 |
1 |
|
T141 |
1 |
|
T150 |
1 |
|
T317 |
1 |
| true |
432 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T54 |
1 |
|
T241 |
1 |
|
T262 |
1 |
| others[1] |
1258 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T315 |
1 |
| others[2] |
1236 |
1 |
|
T142 |
1 |
|
T296 |
1 |
|
T1 |
1 |
| others[3] |
2088 |
1 |
|
T61 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| false |
638 |
1 |
|
T193 |
1 |
|
T1 |
1 |
|
T6 |
3 |
| true |
408 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T25 |
3 |
|
T46 |
7 |
|
T88 |
1 |
| others[1] |
90 |
1 |
|
T25 |
2 |
|
T46 |
4 |
|
T348 |
1 |
| others[2] |
111 |
1 |
|
T23 |
4 |
|
T25 |
1 |
|
T46 |
6 |
| others[3] |
197 |
1 |
|
T1 |
1 |
|
T23 |
3 |
|
T25 |
12 |
| false |
50 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
1 |
| true |
6328 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T23 |
3 |
|
T27 |
1 |
|
T25 |
10 |
| others[1] |
261 |
1 |
|
T1 |
1 |
|
T25 |
12 |
|
T46 |
10 |
| others[2] |
228 |
1 |
|
T25 |
8 |
|
T46 |
12 |
|
T28 |
1 |
| others[3] |
378 |
1 |
|
T23 |
2 |
|
T25 |
16 |
|
T46 |
20 |
| false |
135 |
1 |
|
T25 |
11 |
|
T46 |
5 |
|
T127 |
3 |
| true |
5623 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1068 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T139 |
1 |
| others[1] |
1121 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T144 |
1 |
| others[2] |
1043 |
1 |
|
T244 |
1 |
|
T343 |
1 |
|
T346 |
1 |
| others[3] |
1729 |
1 |
|
T193 |
1 |
|
T297 |
1 |
|
T149 |
1 |
| false |
560 |
1 |
|
T141 |
1 |
|
T142 |
1 |
|
T143 |
1 |
| true |
1348 |
1 |
|
T49 |
1 |
|
T8 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
8 |
| others[1] |
253 |
1 |
|
T23 |
1 |
|
T25 |
20 |
|
T46 |
7 |
| others[2] |
228 |
1 |
|
T27 |
1 |
|
T25 |
8 |
|
T46 |
11 |
| others[3] |
400 |
1 |
|
T23 |
3 |
|
T25 |
18 |
|
T46 |
18 |
| false |
112 |
1 |
|
T23 |
1 |
|
T25 |
1 |
|
T46 |
5 |
| true |
5637 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T25 |
9 |
|
T46 |
9 |
|
T348 |
1 |
| others[1] |
244 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
13 |
| others[2] |
220 |
1 |
|
T25 |
12 |
|
T46 |
9 |
|
T65 |
1 |
| others[3] |
355 |
1 |
|
T23 |
1 |
|
T27 |
1 |
|
T25 |
16 |
| false |
125 |
1 |
|
T23 |
1 |
|
T25 |
1 |
|
T46 |
7 |
| true |
5691 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1227 |
1 |
|
T61 |
1 |
|
T141 |
1 |
|
T142 |
1 |
| others[1] |
1256 |
1 |
|
T297 |
1 |
|
T145 |
1 |
|
T239 |
1 |
| others[2] |
1237 |
1 |
|
T140 |
1 |
|
T193 |
1 |
|
T349 |
1 |
| others[3] |
2104 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T143 |
1 |
| false |
616 |
1 |
|
T139 |
1 |
|
T296 |
1 |
|
T149 |
1 |
| true |
429 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |