Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T146 |
1 |
|
T349 |
1 |
|
T317 |
1 |
| others[1] |
1187 |
1 |
|
T141 |
1 |
|
T144 |
1 |
|
T241 |
1 |
| others[2] |
1246 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T140 |
1 |
| others[3] |
2149 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T193 |
1 |
| false |
620 |
1 |
|
T142 |
1 |
|
T239 |
1 |
|
T150 |
1 |
| true |
411 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
3 |
| others[1] |
103 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
1 |
| others[2] |
87 |
1 |
|
T23 |
2 |
|
T25 |
4 |
|
T46 |
4 |
| others[3] |
174 |
1 |
|
T1 |
1 |
|
T23 |
3 |
|
T25 |
5 |
| false |
60 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
3 |
| true |
6345 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
6 |
| others[1] |
234 |
1 |
|
T25 |
9 |
|
T46 |
6 |
|
T48 |
1 |
| others[2] |
266 |
1 |
|
T25 |
11 |
|
T46 |
8 |
|
T39 |
1 |
| others[3] |
406 |
1 |
|
T23 |
1 |
|
T25 |
18 |
|
T46 |
14 |
| false |
116 |
1 |
|
T23 |
1 |
|
T25 |
5 |
|
T46 |
4 |
| true |
5602 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T142 |
1 |
| others[1] |
1049 |
1 |
|
T315 |
1 |
|
T146 |
1 |
|
T343 |
1 |
| others[2] |
1073 |
1 |
|
T147 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| others[3] |
1769 |
1 |
|
T61 |
1 |
|
T139 |
1 |
|
T141 |
1 |
| false |
567 |
1 |
|
T244 |
1 |
|
T341 |
1 |
|
T6 |
6 |
| true |
1374 |
1 |
|
T12 |
1 |
|
T45 |
1 |
|
T65 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T23 |
1 |
|
T25 |
8 |
|
T46 |
9 |
| others[1] |
229 |
1 |
|
T1 |
1 |
|
T25 |
14 |
|
T46 |
11 |
| others[2] |
218 |
1 |
|
T23 |
1 |
|
T27 |
1 |
|
T25 |
9 |
| others[3] |
405 |
1 |
|
T23 |
1 |
|
T25 |
18 |
|
T46 |
14 |
| false |
138 |
1 |
|
T23 |
1 |
|
T25 |
8 |
|
T46 |
11 |
| true |
5661 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T25 |
13 |
|
T46 |
11 |
|
T350 |
1 |
| others[1] |
201 |
1 |
|
T27 |
1 |
|
T25 |
11 |
|
T46 |
7 |
| others[2] |
209 |
1 |
|
T23 |
1 |
|
T25 |
5 |
|
T46 |
8 |
| others[3] |
386 |
1 |
|
T23 |
3 |
|
T25 |
16 |
|
T46 |
21 |
| false |
125 |
1 |
|
T25 |
4 |
|
T46 |
5 |
|
T76 |
1 |
| true |
5744 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T315 |
1 |
| others[1] |
1256 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T143 |
1 |
| others[2] |
1209 |
1 |
|
T193 |
1 |
|
T145 |
1 |
|
T241 |
1 |
| others[3] |
2068 |
1 |
|
T139 |
1 |
|
T144 |
1 |
|
T239 |
1 |
| false |
641 |
1 |
|
T61 |
1 |
|
T142 |
1 |
|
T296 |
1 |
| true |
429 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1268 |
1 |
|
T140 |
1 |
|
T144 |
1 |
|
T316 |
1 |
| others[1] |
1199 |
1 |
|
T141 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| others[2] |
1247 |
1 |
|
T61 |
1 |
|
T297 |
1 |
|
T239 |
1 |
| others[3] |
2089 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T139 |
1 |
| false |
649 |
1 |
|
T142 |
1 |
|
T315 |
1 |
|
T145 |
1 |
| true |
417 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
3 |
| others[1] |
117 |
1 |
|
T23 |
3 |
|
T25 |
3 |
|
T46 |
4 |
| others[2] |
111 |
1 |
|
T1 |
1 |
|
T25 |
5 |
|
T46 |
6 |
| others[3] |
172 |
1 |
|
T23 |
3 |
|
T27 |
1 |
|
T25 |
2 |
| false |
49 |
1 |
|
T23 |
1 |
|
T25 |
3 |
|
T46 |
3 |
| true |
6315 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T23 |
2 |
|
T25 |
7 |
|
T46 |
13 |
| others[1] |
227 |
1 |
|
T25 |
6 |
|
T46 |
9 |
|
T351 |
1 |
| others[2] |
234 |
1 |
|
T23 |
1 |
|
T25 |
7 |
|
T46 |
10 |
| others[3] |
364 |
1 |
|
T23 |
2 |
|
T25 |
20 |
|
T46 |
17 |
| false |
114 |
1 |
|
T23 |
1 |
|
T25 |
3 |
|
T46 |
4 |
| true |
5692 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1042 |
1 |
|
T61 |
1 |
|
T343 |
1 |
|
T262 |
1 |
| others[1] |
1075 |
1 |
|
T142 |
1 |
|
T239 |
1 |
|
T241 |
1 |
| others[2] |
1050 |
1 |
|
T145 |
1 |
|
T316 |
1 |
|
T341 |
1 |
| others[3] |
1836 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T140 |
1 |
| false |
505 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T345 |
1 |
| true |
1361 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T45 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T25 |
14 |
|
T46 |
7 |
|
T40 |
2 |
| others[1] |
227 |
1 |
|
T25 |
10 |
|
T46 |
8 |
|
T40 |
1 |
| others[2] |
266 |
1 |
|
T23 |
2 |
|
T25 |
13 |
|
T46 |
11 |
| others[3] |
397 |
1 |
|
T23 |
1 |
|
T25 |
18 |
|
T46 |
15 |
| false |
112 |
1 |
|
T25 |
2 |
|
T46 |
5 |
|
T40 |
1 |
| true |
5634 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T23 |
1 |
|
T25 |
11 |
|
T46 |
12 |
| others[1] |
218 |
1 |
|
T1 |
1 |
|
T27 |
1 |
|
T25 |
8 |
| others[2] |
233 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T25 |
12 |
| others[3] |
363 |
1 |
|
T25 |
15 |
|
T46 |
17 |
|
T256 |
1 |
| false |
126 |
1 |
|
T25 |
8 |
|
T46 |
5 |
|
T88 |
1 |
| true |
5702 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1293 |
1 |
|
T142 |
1 |
|
T144 |
1 |
|
T349 |
1 |
| others[1] |
1229 |
1 |
|
T54 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| others[2] |
1194 |
1 |
|
T297 |
1 |
|
T146 |
1 |
|
T316 |
1 |
| others[3] |
2094 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T139 |
1 |
| false |
641 |
1 |
|
T150 |
1 |
|
T317 |
1 |
|
T347 |
1 |
| true |
418 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T315 |
1 |
| others[1] |
1232 |
1 |
|
T149 |
1 |
|
T244 |
1 |
|
T316 |
1 |
| others[2] |
1255 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T193 |
1 |
| others[3] |
2068 |
1 |
|
T61 |
1 |
|
T142 |
1 |
|
T150 |
1 |
| false |
661 |
1 |
|
T54 |
1 |
|
T241 |
1 |
|
T349 |
1 |
| true |
415 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T23 |
4 |
|
T25 |
3 |
|
T46 |
2 |
| others[1] |
108 |
1 |
|
T23 |
1 |
|
T25 |
6 |
|
T46 |
4 |
| others[2] |
123 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
4 |
| others[3] |
161 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
6 |
| false |
49 |
1 |
|
T23 |
1 |
|
T25 |
2 |
|
T46 |
1 |
| true |
6318 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T25 |
6 |
|
T46 |
8 |
|
T48 |
1 |
| others[1] |
238 |
1 |
|
T23 |
1 |
|
T25 |
12 |
|
T46 |
12 |
| others[2] |
244 |
1 |
|
T25 |
6 |
|
T46 |
9 |
|
T40 |
1 |
| others[3] |
404 |
1 |
|
T25 |
18 |
|
T46 |
16 |
|
T39 |
1 |
| false |
121 |
1 |
|
T25 |
7 |
|
T46 |
2 |
|
T256 |
1 |
| true |
5631 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1100 |
1 |
|
T142 |
1 |
|
T193 |
1 |
|
T296 |
1 |
| others[1] |
1081 |
1 |
|
T140 |
1 |
|
T239 |
1 |
|
T344 |
1 |
| others[2] |
977 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T139 |
1 |
| others[3] |
1829 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T143 |
1 |
| false |
557 |
1 |
|
T315 |
1 |
|
T244 |
1 |
|
T317 |
1 |
| true |
1325 |
1 |
|
T49 |
1 |
|
T53 |
1 |
|
T45 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T25 |
7 |
|
T46 |
6 |
|
T65 |
1 |
| others[1] |
246 |
1 |
|
T1 |
2 |
|
T23 |
1 |
|
T25 |
10 |
| others[2] |
194 |
1 |
|
T23 |
3 |
|
T25 |
8 |
|
T46 |
4 |
| others[3] |
389 |
1 |
|
T25 |
20 |
|
T46 |
23 |
|
T68 |
1 |
| false |
132 |
1 |
|
T23 |
1 |
|
T27 |
1 |
|
T25 |
7 |
| true |
5674 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T23 |
1 |
|
T25 |
10 |
|
T46 |
13 |
| others[1] |
204 |
1 |
|
T1 |
1 |
|
T25 |
6 |
|
T46 |
5 |
| others[2] |
216 |
1 |
|
T23 |
2 |
|
T25 |
13 |
|
T46 |
10 |
| others[3] |
390 |
1 |
|
T23 |
4 |
|
T8 |
1 |
|
T25 |
17 |
| false |
116 |
1 |
|
T25 |
6 |
|
T46 |
8 |
|
T127 |
8 |
| true |
5695 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1225 |
1 |
|
T140 |
1 |
|
T193 |
1 |
|
T315 |
1 |
| others[1] |
1248 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T142 |
1 |
| others[2] |
1204 |
1 |
|
T61 |
1 |
|
T143 |
1 |
|
T296 |
1 |
| others[3] |
2092 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T144 |
1 |
| false |
674 |
1 |
|
T316 |
1 |
|
T345 |
1 |
|
T22 |
1 |
| true |
426 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1267 |
1 |
|
T61 |
1 |
|
T193 |
1 |
|
T297 |
1 |
| others[1] |
1256 |
1 |
|
T142 |
1 |
|
T143 |
1 |
|
T315 |
1 |
| others[2] |
1255 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T145 |
1 |
| others[3] |
2028 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T241 |
1 |
| false |
637 |
1 |
|
T139 |
1 |
|
T239 |
1 |
|
T150 |
1 |
| true |
426 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
97 |
1 |
|
T25 |
3 |
|
T46 |
4 |
|
T348 |
1 |
| others[1] |
104 |
1 |
|
T23 |
1 |
|
T25 |
1 |
|
T46 |
2 |
| others[2] |
116 |
1 |
|
T1 |
1 |
|
T23 |
4 |
|
T25 |
3 |
| others[3] |
161 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
4 |
| false |
57 |
1 |
|
T23 |
1 |
|
T96 |
2 |
|
T353 |
1 |
| true |
6334 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T23 |
1 |
|
T25 |
16 |
|
T46 |
3 |
| others[1] |
235 |
1 |
|
T25 |
8 |
|
T46 |
14 |
|
T65 |
1 |
| others[2] |
217 |
1 |
|
T25 |
14 |
|
T46 |
10 |
|
T342 |
1 |
| others[3] |
400 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
13 |
| false |
117 |
1 |
|
T1 |
1 |
|
T25 |
3 |
|
T46 |
3 |
| true |
5650 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1062 |
1 |
|
T145 |
1 |
|
T239 |
1 |
|
T349 |
1 |
| others[1] |
1086 |
1 |
|
T141 |
1 |
|
T142 |
1 |
|
T296 |
1 |
| others[2] |
1046 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T193 |
1 |
| others[3] |
1712 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T143 |
1 |
| false |
555 |
1 |
|
T139 |
1 |
|
T144 |
1 |
|
T241 |
1 |
| true |
1408 |
1 |
|
T8 |
1 |
|
T53 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T27 |
1 |
|
T25 |
8 |
|
T46 |
9 |
| others[1] |
248 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
11 |
| others[2] |
236 |
1 |
|
T23 |
1 |
|
T25 |
5 |
|
T46 |
10 |
| others[3] |
392 |
1 |
|
T1 |
1 |
|
T25 |
15 |
|
T46 |
16 |
| false |
136 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
7 |
| true |
5653 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T23 |
1 |
|
T25 |
8 |
|
T46 |
10 |
| others[1] |
209 |
1 |
|
T23 |
1 |
|
T25 |
10 |
|
T46 |
8 |
| others[2] |
234 |
1 |
|
T27 |
1 |
|
T25 |
18 |
|
T46 |
6 |
| others[3] |
372 |
1 |
|
T25 |
13 |
|
T46 |
16 |
|
T348 |
1 |
| false |
99 |
1 |
|
T25 |
1 |
|
T46 |
4 |
|
T65 |
1 |
| true |
5732 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T147 |
1 |
|
T241 |
1 |
|
T265 |
1 |
| others[1] |
1258 |
1 |
|
T139 |
1 |
|
T140 |
1 |
|
T141 |
1 |
| others[2] |
1224 |
1 |
|
T61 |
1 |
|
T145 |
1 |
|
T316 |
1 |
| others[3] |
2077 |
1 |
|
T54 |
1 |
|
T142 |
1 |
|
T143 |
1 |
| false |
641 |
1 |
|
T296 |
1 |
|
T6 |
7 |
|
T23 |
1 |
| true |
432 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1327 |
1 |
|
T61 |
1 |
|
T140 |
1 |
|
T239 |
1 |
| others[1] |
1195 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T193 |
1 |
| others[2] |
1226 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T143 |
1 |
| others[3] |
2069 |
1 |
|
T142 |
1 |
|
T241 |
1 |
|
T316 |
1 |
| false |
628 |
1 |
|
T144 |
1 |
|
T244 |
1 |
|
T6 |
4 |
| true |
424 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
3 |
| others[1] |
104 |
1 |
|
T23 |
4 |
|
T25 |
3 |
|
T46 |
4 |
| others[2] |
108 |
1 |
|
T23 |
1 |
|
T25 |
2 |
|
T46 |
6 |
| others[3] |
202 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
6 |
| false |
57 |
1 |
|
T23 |
1 |
|
T25 |
1 |
|
T46 |
3 |
| true |
6294 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T25 |
9 |
| others[1] |
245 |
1 |
|
T23 |
1 |
|
T25 |
5 |
|
T46 |
10 |
| others[2] |
224 |
1 |
|
T25 |
7 |
|
T46 |
8 |
|
T68 |
1 |
| others[3] |
409 |
1 |
|
T23 |
1 |
|
T27 |
1 |
|
T25 |
18 |
| false |
119 |
1 |
|
T1 |
1 |
|
T25 |
5 |
|
T46 |
3 |
| true |
5633 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |