Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1073 |
1 |
|
T139 |
1 |
|
T239 |
1 |
|
T316 |
1 |
| others[1] |
1029 |
1 |
|
T54 |
1 |
|
T296 |
1 |
|
T145 |
1 |
| others[2] |
1059 |
1 |
|
T141 |
1 |
|
T142 |
1 |
|
T150 |
1 |
| others[3] |
1751 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T140 |
1 |
| false |
556 |
1 |
|
T315 |
1 |
|
T6 |
6 |
|
T25 |
7 |
| true |
1401 |
1 |
|
T12 |
1 |
|
T53 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T23 |
3 |
|
T25 |
9 |
|
T46 |
12 |
| others[1] |
243 |
1 |
|
T25 |
12 |
|
T46 |
7 |
|
T123 |
1 |
| others[2] |
224 |
1 |
|
T8 |
1 |
|
T25 |
10 |
|
T46 |
11 |
| others[3] |
391 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
11 |
| false |
124 |
1 |
|
T25 |
3 |
|
T46 |
8 |
|
T121 |
1 |
| true |
5680 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T25 |
14 |
| others[1] |
219 |
1 |
|
T25 |
7 |
|
T46 |
4 |
|
T342 |
1 |
| others[2] |
224 |
1 |
|
T27 |
1 |
|
T25 |
9 |
|
T46 |
10 |
| others[3] |
383 |
1 |
|
T1 |
1 |
|
T23 |
3 |
|
T25 |
14 |
| false |
99 |
1 |
|
T25 |
3 |
|
T46 |
6 |
|
T342 |
1 |
| true |
5716 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T140 |
1 |
|
T241 |
1 |
|
T150 |
1 |
| others[1] |
1234 |
1 |
|
T141 |
1 |
|
T142 |
1 |
|
T315 |
1 |
| others[2] |
1289 |
1 |
|
T144 |
1 |
|
T145 |
1 |
|
T149 |
1 |
| others[3] |
2028 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
| false |
639 |
1 |
|
T297 |
1 |
|
T6 |
9 |
|
T23 |
1 |
| true |
432 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1237 |
1 |
|
T315 |
1 |
|
T343 |
1 |
|
T344 |
1 |
| others[1] |
1236 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T144 |
1 |
| others[2] |
1231 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T143 |
1 |
| others[3] |
2093 |
1 |
|
T139 |
1 |
|
T140 |
1 |
|
T142 |
1 |
| false |
662 |
1 |
|
T316 |
1 |
|
T150 |
1 |
|
T341 |
1 |
| true |
410 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
3 |
| others[1] |
106 |
1 |
|
T23 |
1 |
|
T25 |
3 |
|
T46 |
3 |
| others[2] |
110 |
1 |
|
T23 |
2 |
|
T25 |
4 |
|
T348 |
1 |
| others[3] |
185 |
1 |
|
T1 |
2 |
|
T23 |
4 |
|
T25 |
10 |
| false |
66 |
1 |
|
T25 |
1 |
|
T46 |
7 |
|
T342 |
1 |
| true |
6299 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T25 |
11 |
|
T46 |
11 |
|
T76 |
1 |
| others[1] |
245 |
1 |
|
T25 |
11 |
|
T46 |
13 |
|
T342 |
1 |
| others[2] |
226 |
1 |
|
T23 |
2 |
|
T25 |
10 |
|
T46 |
6 |
| others[3] |
411 |
1 |
|
T23 |
2 |
|
T25 |
13 |
|
T46 |
16 |
| false |
106 |
1 |
|
T25 |
4 |
|
T46 |
7 |
|
T348 |
1 |
| true |
5647 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1036 |
1 |
|
T315 |
1 |
|
T144 |
1 |
|
T297 |
1 |
| others[1] |
1050 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| others[2] |
1023 |
1 |
|
T61 |
1 |
|
T150 |
1 |
|
T345 |
1 |
| others[3] |
1807 |
1 |
|
T54 |
1 |
|
T193 |
1 |
|
T296 |
1 |
| false |
562 |
1 |
|
T141 |
1 |
|
T142 |
1 |
|
T241 |
1 |
| true |
1391 |
1 |
|
T49 |
1 |
|
T45 |
1 |
|
T65 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T1 |
1 |
|
T25 |
9 |
|
T46 |
10 |
| others[1] |
260 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
12 |
| others[2] |
229 |
1 |
|
T27 |
1 |
|
T25 |
5 |
|
T46 |
10 |
| others[3] |
431 |
1 |
|
T23 |
1 |
|
T25 |
18 |
|
T46 |
25 |
| false |
119 |
1 |
|
T23 |
1 |
|
T25 |
7 |
|
T46 |
6 |
| true |
5625 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T1 |
2 |
|
T23 |
1 |
|
T25 |
12 |
| others[1] |
227 |
1 |
|
T23 |
2 |
|
T25 |
4 |
|
T46 |
9 |
| others[2] |
241 |
1 |
|
T23 |
1 |
|
T25 |
10 |
|
T46 |
11 |
| others[3] |
350 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T25 |
15 |
| false |
121 |
1 |
|
T25 |
7 |
|
T46 |
6 |
|
T127 |
5 |
| true |
5712 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T315 |
1 |
|
T241 |
1 |
|
T244 |
1 |
| others[1] |
1275 |
1 |
|
T143 |
1 |
|
T296 |
1 |
|
T297 |
1 |
| others[2] |
1222 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T317 |
1 |
| others[3] |
2079 |
1 |
|
T61 |
1 |
|
T139 |
1 |
|
T142 |
1 |
| false |
643 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T6 |
7 |
| true |
432 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T145 |
1 |
| others[1] |
1261 |
1 |
|
T139 |
1 |
|
T142 |
1 |
|
T144 |
1 |
| others[2] |
1255 |
1 |
|
T61 |
1 |
|
T146 |
1 |
|
T316 |
1 |
| others[3] |
2062 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T193 |
1 |
| false |
625 |
1 |
|
T241 |
1 |
|
T244 |
1 |
|
T265 |
1 |
| true |
415 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T25 |
4 |
|
T46 |
7 |
|
T342 |
1 |
| others[1] |
120 |
1 |
|
T1 |
1 |
|
T23 |
4 |
|
T25 |
6 |
| others[2] |
107 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
6 |
| others[3] |
167 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
7 |
| false |
65 |
1 |
|
T23 |
2 |
|
T25 |
3 |
|
T46 |
5 |
| true |
6308 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T23 |
1 |
|
T25 |
8 |
|
T46 |
14 |
| others[1] |
214 |
1 |
|
T23 |
1 |
|
T25 |
8 |
|
T46 |
7 |
| others[2] |
256 |
1 |
|
T23 |
1 |
|
T25 |
9 |
|
T46 |
10 |
| others[3] |
427 |
1 |
|
T25 |
16 |
|
T46 |
18 |
|
T123 |
1 |
| false |
126 |
1 |
|
T8 |
1 |
|
T25 |
3 |
|
T46 |
7 |
| true |
5602 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1079 |
1 |
|
T139 |
1 |
|
T145 |
1 |
|
T239 |
1 |
| others[1] |
1075 |
1 |
|
T61 |
1 |
|
T296 |
1 |
|
T149 |
1 |
| others[2] |
1076 |
1 |
|
T147 |
1 |
|
T142 |
1 |
|
T345 |
1 |
| others[3] |
1728 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T141 |
1 |
| false |
529 |
1 |
|
T297 |
1 |
|
T347 |
1 |
|
T6 |
4 |
| true |
1382 |
1 |
|
T49 |
1 |
|
T8 |
1 |
|
T65 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
5 |
| others[1] |
238 |
1 |
|
T25 |
13 |
|
T46 |
13 |
|
T354 |
1 |
| others[2] |
229 |
1 |
|
T23 |
1 |
|
T27 |
1 |
|
T25 |
10 |
| others[3] |
357 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T8 |
1 |
| false |
114 |
1 |
|
T25 |
2 |
|
T46 |
6 |
|
T207 |
1 |
| true |
5713 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T25 |
9 |
|
T46 |
9 |
|
T348 |
1 |
| others[1] |
221 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
10 |
| others[2] |
202 |
1 |
|
T25 |
3 |
|
T46 |
12 |
|
T121 |
1 |
| others[3] |
382 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T27 |
1 |
| false |
122 |
1 |
|
T25 |
4 |
|
T46 |
6 |
|
T127 |
7 |
| true |
5720 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T296 |
1 |
|
T297 |
1 |
|
T145 |
1 |
| others[1] |
1236 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T193 |
1 |
| others[2] |
1219 |
1 |
|
T141 |
1 |
|
T241 |
1 |
|
T349 |
1 |
| others[3] |
2111 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T140 |
1 |
| false |
628 |
1 |
|
T146 |
1 |
|
T317 |
1 |
|
T345 |
1 |
| true |
429 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1274 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T22 |
1 |
| others[1] |
1223 |
1 |
|
T193 |
1 |
|
T297 |
1 |
|
T150 |
1 |
| others[2] |
1258 |
1 |
|
T145 |
1 |
|
T241 |
1 |
|
T349 |
1 |
| others[3] |
2030 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| false |
667 |
1 |
|
T144 |
1 |
|
T149 |
1 |
|
T316 |
1 |
| true |
417 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T23 |
2 |
|
T25 |
1 |
|
T46 |
4 |
| others[1] |
120 |
1 |
|
T1 |
1 |
|
T23 |
3 |
|
T25 |
5 |
| others[2] |
116 |
1 |
|
T23 |
1 |
|
T25 |
3 |
|
T46 |
7 |
| others[3] |
176 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
4 |
| false |
55 |
1 |
|
T25 |
4 |
|
T46 |
2 |
|
T342 |
1 |
| true |
6296 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T23 |
1 |
|
T27 |
1 |
|
T25 |
7 |
| others[1] |
217 |
1 |
|
T23 |
1 |
|
T25 |
10 |
|
T46 |
11 |
| others[2] |
248 |
1 |
|
T23 |
1 |
|
T25 |
11 |
|
T46 |
9 |
| others[3] |
394 |
1 |
|
T23 |
1 |
|
T25 |
20 |
|
T46 |
14 |
| false |
135 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
3 |
| true |
5650 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T144 |
1 |
|
T244 |
1 |
|
T347 |
1 |
| others[1] |
1111 |
1 |
|
T139 |
1 |
|
T193 |
1 |
|
T315 |
1 |
| others[2] |
1010 |
1 |
|
T61 |
1 |
|
T142 |
1 |
|
T143 |
1 |
| others[3] |
1729 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T140 |
1 |
| false |
560 |
1 |
|
T297 |
1 |
|
T145 |
1 |
|
T265 |
1 |
| true |
1396 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T25 |
7 |
|
T46 |
10 |
|
T342 |
1 |
| others[1] |
230 |
1 |
|
T23 |
2 |
|
T8 |
1 |
|
T25 |
13 |
| others[2] |
244 |
1 |
|
T25 |
8 |
|
T46 |
11 |
|
T123 |
1 |
| others[3] |
409 |
1 |
|
T23 |
1 |
|
T27 |
1 |
|
T25 |
15 |
| false |
138 |
1 |
|
T25 |
11 |
|
T46 |
4 |
|
T348 |
1 |
| true |
5621 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T25 |
8 |
| others[1] |
223 |
1 |
|
T1 |
1 |
|
T25 |
13 |
|
T46 |
10 |
| others[2] |
194 |
1 |
|
T23 |
2 |
|
T25 |
5 |
|
T46 |
12 |
| others[3] |
416 |
1 |
|
T23 |
1 |
|
T25 |
25 |
|
T46 |
14 |
| false |
120 |
1 |
|
T1 |
1 |
|
T25 |
4 |
|
T46 |
5 |
| true |
5696 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1266 |
1 |
|
T147 |
1 |
|
T142 |
1 |
|
T145 |
1 |
| others[1] |
1241 |
1 |
|
T61 |
1 |
|
T297 |
1 |
|
T241 |
1 |
| others[2] |
1243 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T315 |
1 |
| others[3] |
2056 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T143 |
1 |
| false |
623 |
1 |
|
T193 |
1 |
|
T239 |
1 |
|
T244 |
1 |
| true |
440 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1183 |
1 |
|
T54 |
1 |
|
T315 |
1 |
|
T297 |
1 |
| others[1] |
1238 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T142 |
1 |
| others[2] |
1268 |
1 |
|
T61 |
1 |
|
T139 |
1 |
|
T141 |
1 |
| others[3] |
2122 |
1 |
|
T193 |
1 |
|
T144 |
1 |
|
T239 |
1 |
| false |
641 |
1 |
|
T20 |
1 |
|
T6 |
6 |
|
T25 |
9 |
| true |
417 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
3 |
| others[1] |
106 |
1 |
|
T23 |
2 |
|
T25 |
4 |
|
T46 |
7 |
| others[2] |
112 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T27 |
1 |
| others[3] |
168 |
1 |
|
T23 |
2 |
|
T25 |
7 |
|
T46 |
10 |
| false |
65 |
1 |
|
T25 |
2 |
|
T46 |
2 |
|
T348 |
1 |
| true |
6313 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T23 |
2 |
|
T25 |
6 |
|
T46 |
10 |
| others[1] |
241 |
1 |
|
T25 |
14 |
|
T46 |
10 |
|
T348 |
1 |
| others[2] |
230 |
1 |
|
T27 |
1 |
|
T25 |
2 |
|
T46 |
8 |
| others[3] |
402 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
17 |
| false |
112 |
1 |
|
T23 |
1 |
|
T25 |
11 |
|
T46 |
4 |
| true |
5651 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1087 |
1 |
|
T139 |
1 |
|
T146 |
1 |
|
T349 |
1 |
| others[1] |
1085 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T144 |
1 |
| others[2] |
1083 |
1 |
|
T61 |
1 |
|
T193 |
1 |
|
T315 |
1 |
| others[3] |
1740 |
1 |
|
T141 |
1 |
|
T142 |
1 |
|
T143 |
1 |
| false |
537 |
1 |
|
T147 |
1 |
|
T341 |
1 |
|
T6 |
6 |
| true |
1337 |
1 |
|
T45 |
1 |
|
T39 |
1 |
|
T48 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T25 |
15 |
|
T46 |
9 |
|
T48 |
1 |
| others[1] |
259 |
1 |
|
T25 |
10 |
|
T46 |
6 |
|
T39 |
1 |
| others[2] |
188 |
1 |
|
T23 |
1 |
|
T25 |
3 |
|
T46 |
7 |
| others[3] |
365 |
1 |
|
T23 |
1 |
|
T25 |
17 |
|
T46 |
15 |
| false |
135 |
1 |
|
T25 |
5 |
|
T46 |
7 |
|
T65 |
1 |
| true |
5684 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T23 |
2 |
|
T25 |
7 |
|
T46 |
11 |
| others[1] |
223 |
1 |
|
T23 |
1 |
|
T25 |
14 |
|
T46 |
6 |
| others[2] |
200 |
1 |
|
T25 |
7 |
|
T46 |
5 |
|
T351 |
1 |
| others[3] |
379 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
11 |
| false |
96 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
1 |
| true |
5741 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |