Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1187 |
1 |
|
T142 |
1 |
|
T315 |
1 |
|
T265 |
1 |
| others[1] |
1283 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T140 |
1 |
| others[2] |
1229 |
1 |
|
T54 |
1 |
|
T297 |
1 |
|
T146 |
1 |
| others[3] |
2063 |
1 |
|
T139 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| false |
677 |
1 |
|
T144 |
1 |
|
T239 |
1 |
|
T345 |
1 |
| true |
430 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T146 |
1 |
|
T316 |
1 |
|
T262 |
1 |
| others[1] |
1229 |
1 |
|
T61 |
1 |
|
T143 |
1 |
|
T296 |
1 |
| others[2] |
1242 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T193 |
1 |
| others[3] |
2103 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| false |
694 |
1 |
|
T142 |
1 |
|
T6 |
3 |
|
T23 |
1 |
| true |
419 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
124 |
1 |
|
T23 |
2 |
|
T25 |
1 |
|
T46 |
1 |
| others[1] |
117 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
6 |
| others[2] |
108 |
1 |
|
T1 |
1 |
|
T23 |
3 |
|
T25 |
2 |
| others[3] |
175 |
1 |
|
T23 |
1 |
|
T25 |
9 |
|
T46 |
4 |
| false |
53 |
1 |
|
T23 |
1 |
|
T25 |
1 |
|
T46 |
1 |
| true |
6292 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T25 |
18 |
|
T46 |
10 |
|
T39 |
1 |
| others[1] |
212 |
1 |
|
T25 |
10 |
|
T46 |
13 |
|
T68 |
1 |
| others[2] |
237 |
1 |
|
T27 |
1 |
|
T25 |
8 |
|
T46 |
8 |
| others[3] |
428 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
13 |
| false |
127 |
1 |
|
T25 |
4 |
|
T46 |
5 |
|
T127 |
8 |
| true |
5618 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1055 |
1 |
|
T193 |
1 |
|
T143 |
1 |
|
T144 |
1 |
| others[1] |
1073 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T146 |
1 |
| others[2] |
1053 |
1 |
|
T142 |
1 |
|
T239 |
1 |
|
T149 |
1 |
| others[3] |
1778 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
| false |
560 |
1 |
|
T315 |
1 |
|
T145 |
1 |
|
T150 |
1 |
| true |
1350 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T25 |
9 |
|
T46 |
6 |
|
T121 |
1 |
| others[1] |
221 |
1 |
|
T1 |
1 |
|
T25 |
10 |
|
T46 |
12 |
| others[2] |
242 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
11 |
| others[3] |
404 |
1 |
|
T23 |
2 |
|
T25 |
9 |
|
T46 |
19 |
| false |
120 |
1 |
|
T23 |
1 |
|
T25 |
8 |
|
T46 |
3 |
| true |
5640 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T23 |
3 |
|
T25 |
12 |
|
T46 |
13 |
| others[1] |
235 |
1 |
|
T23 |
1 |
|
T25 |
10 |
|
T46 |
3 |
| others[2] |
219 |
1 |
|
T25 |
9 |
|
T46 |
7 |
|
T76 |
1 |
| others[3] |
370 |
1 |
|
T23 |
1 |
|
T8 |
1 |
|
T25 |
14 |
| false |
133 |
1 |
|
T27 |
1 |
|
T25 |
3 |
|
T46 |
2 |
| true |
5686 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T193 |
1 |
| others[1] |
1213 |
1 |
|
T141 |
1 |
|
T239 |
1 |
|
T241 |
1 |
| others[2] |
1217 |
1 |
|
T144 |
1 |
|
T296 |
1 |
|
T297 |
1 |
| others[3] |
2086 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T142 |
1 |
| false |
671 |
1 |
|
T140 |
1 |
|
T244 |
1 |
|
T1 |
1 |
| true |
440 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T61 |
1 |
|
T193 |
1 |
|
T146 |
1 |
| others[1] |
1225 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T297 |
1 |
| others[2] |
1267 |
1 |
|
T54 |
1 |
|
T142 |
1 |
|
T144 |
1 |
| others[3] |
2075 |
1 |
|
T140 |
1 |
|
T141 |
1 |
|
T143 |
1 |
| false |
645 |
1 |
|
T244 |
1 |
|
T4 |
1 |
|
T6 |
1 |
| true |
418 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T27 |
1 |
|
T25 |
6 |
|
T46 |
4 |
| others[1] |
105 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
3 |
| others[2] |
117 |
1 |
|
T23 |
3 |
|
T25 |
4 |
|
T46 |
4 |
| others[3] |
175 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
8 |
| false |
59 |
1 |
|
T23 |
1 |
|
T25 |
3 |
|
T46 |
1 |
| true |
6298 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T23 |
1 |
|
T25 |
5 |
|
T46 |
4 |
| others[1] |
262 |
1 |
|
T1 |
1 |
|
T25 |
15 |
|
T46 |
7 |
| others[2] |
215 |
1 |
|
T25 |
10 |
|
T46 |
13 |
|
T40 |
2 |
| others[3] |
406 |
1 |
|
T23 |
2 |
|
T8 |
1 |
|
T25 |
14 |
| false |
107 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
4 |
| true |
5644 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1030 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T315 |
1 |
| others[1] |
1054 |
1 |
|
T140 |
1 |
|
T143 |
1 |
|
T239 |
1 |
| others[2] |
1055 |
1 |
|
T61 |
1 |
|
T142 |
1 |
|
T145 |
1 |
| others[3] |
1792 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T193 |
1 |
| false |
568 |
1 |
|
T6 |
4 |
|
T23 |
2 |
|
T25 |
4 |
| true |
1370 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
5 |
| others[1] |
220 |
1 |
|
T25 |
11 |
|
T46 |
6 |
|
T88 |
1 |
| others[2] |
235 |
1 |
|
T25 |
9 |
|
T46 |
15 |
|
T123 |
1 |
| others[3] |
396 |
1 |
|
T27 |
1 |
|
T25 |
17 |
|
T46 |
12 |
| false |
123 |
1 |
|
T1 |
1 |
|
T25 |
5 |
|
T46 |
1 |
| true |
5667 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T23 |
1 |
|
T25 |
13 |
|
T46 |
9 |
| others[1] |
214 |
1 |
|
T23 |
1 |
|
T25 |
9 |
|
T46 |
8 |
| others[2] |
207 |
1 |
|
T27 |
1 |
|
T25 |
6 |
|
T46 |
10 |
| others[3] |
402 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
22 |
| false |
111 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
1 |
| true |
5726 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1279 |
1 |
|
T142 |
1 |
|
T144 |
1 |
|
T241 |
1 |
| others[1] |
1167 |
1 |
|
T315 |
1 |
|
T239 |
1 |
|
T146 |
1 |
| others[2] |
1240 |
1 |
|
T139 |
1 |
|
T140 |
1 |
|
T193 |
1 |
| others[3] |
2063 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
| false |
689 |
1 |
|
T297 |
1 |
|
T145 |
1 |
|
T150 |
1 |
| true |
431 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T61 |
1 |
|
T315 |
1 |
|
T241 |
1 |
| others[1] |
1232 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| others[2] |
1209 |
1 |
|
T142 |
1 |
|
T239 |
1 |
|
T244 |
1 |
| others[3] |
2040 |
1 |
|
T54 |
1 |
|
T143 |
1 |
|
T296 |
1 |
| false |
719 |
1 |
|
T141 |
1 |
|
T193 |
1 |
|
T150 |
1 |
| true |
417 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
123 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
3 |
| others[1] |
99 |
1 |
|
T23 |
1 |
|
T25 |
5 |
|
T348 |
1 |
| others[2] |
102 |
1 |
|
T23 |
3 |
|
T25 |
7 |
|
T127 |
2 |
| others[3] |
176 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
9 |
| false |
59 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
1 |
| true |
6310 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T23 |
1 |
|
T25 |
7 |
|
T46 |
7 |
| others[1] |
247 |
1 |
|
T23 |
2 |
|
T25 |
16 |
|
T46 |
12 |
| others[2] |
241 |
1 |
|
T25 |
8 |
|
T46 |
13 |
|
T127 |
9 |
| others[3] |
425 |
1 |
|
T8 |
1 |
|
T25 |
18 |
|
T46 |
13 |
| false |
127 |
1 |
|
T25 |
7 |
|
T46 |
4 |
|
T69 |
1 |
| true |
5603 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1019 |
1 |
|
T139 |
1 |
|
T143 |
1 |
|
T297 |
1 |
| others[1] |
1027 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T315 |
1 |
| others[2] |
1065 |
1 |
|
T140 |
1 |
|
T144 |
1 |
|
T296 |
1 |
| others[3] |
1811 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T142 |
1 |
| false |
576 |
1 |
|
T193 |
1 |
|
T244 |
1 |
|
T6 |
5 |
| true |
1371 |
1 |
|
T49 |
1 |
|
T8 |
1 |
|
T27 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T23 |
1 |
|
T27 |
1 |
|
T25 |
12 |
| others[1] |
243 |
1 |
|
T25 |
13 |
|
T46 |
5 |
|
T39 |
1 |
| others[2] |
255 |
1 |
|
T1 |
1 |
|
T25 |
5 |
|
T46 |
12 |
| others[3] |
385 |
1 |
|
T25 |
13 |
|
T46 |
21 |
|
T351 |
1 |
| false |
118 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
5 |
| true |
5644 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T25 |
7 |
|
T46 |
12 |
|
T354 |
1 |
| others[1] |
210 |
1 |
|
T23 |
1 |
|
T25 |
9 |
|
T46 |
12 |
| others[2] |
202 |
1 |
|
T23 |
3 |
|
T25 |
6 |
|
T46 |
8 |
| others[3] |
370 |
1 |
|
T23 |
2 |
|
T8 |
1 |
|
T27 |
1 |
| false |
104 |
1 |
|
T1 |
1 |
|
T23 |
2 |
|
T25 |
5 |
| true |
5758 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T54 |
1 |
|
T142 |
1 |
|
T145 |
1 |
| others[1] |
1236 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T149 |
1 |
| others[2] |
1284 |
1 |
|
T143 |
1 |
|
T315 |
1 |
|
T144 |
1 |
| others[3] |
2021 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T140 |
1 |
| false |
641 |
1 |
|
T6 |
3 |
|
T23 |
1 |
|
T25 |
10 |
| true |
438 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1183 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T349 |
1 |
| others[1] |
1288 |
1 |
|
T147 |
1 |
|
T142 |
1 |
|
T143 |
1 |
| others[2] |
1298 |
1 |
|
T139 |
1 |
|
T193 |
1 |
|
T144 |
1 |
| others[3] |
2056 |
1 |
|
T140 |
1 |
|
T141 |
1 |
|
T296 |
1 |
| false |
630 |
1 |
|
T316 |
1 |
|
T1 |
1 |
|
T6 |
4 |
| true |
414 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T1 |
1 |
|
T23 |
3 |
|
T25 |
3 |
| others[1] |
105 |
1 |
|
T23 |
1 |
|
T25 |
8 |
|
T46 |
2 |
| others[2] |
105 |
1 |
|
T23 |
1 |
|
T25 |
7 |
|
T46 |
2 |
| others[3] |
164 |
1 |
|
T1 |
1 |
|
T23 |
3 |
|
T25 |
7 |
| false |
63 |
1 |
|
T25 |
2 |
|
T46 |
1 |
|
T121 |
1 |
| true |
6320 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
268 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
11 |
| others[1] |
213 |
1 |
|
T25 |
9 |
|
T46 |
5 |
|
T256 |
1 |
| others[2] |
234 |
1 |
|
T23 |
2 |
|
T25 |
2 |
|
T46 |
12 |
| others[3] |
371 |
1 |
|
T25 |
13 |
|
T46 |
15 |
|
T76 |
1 |
| false |
123 |
1 |
|
T1 |
1 |
|
T25 |
7 |
|
T46 |
5 |
| true |
5660 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1031 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T296 |
1 |
| others[1] |
1115 |
1 |
|
T61 |
1 |
|
T244 |
1 |
|
T316 |
1 |
| others[2] |
990 |
1 |
|
T140 |
1 |
|
T193 |
1 |
|
T144 |
1 |
| others[3] |
1783 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T142 |
1 |
| false |
581 |
1 |
|
T143 |
1 |
|
T315 |
1 |
|
T239 |
1 |
| true |
1369 |
1 |
|
T53 |
1 |
|
T27 |
1 |
|
T45 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T1 |
1 |
|
T23 |
1 |
|
T25 |
11 |
| others[1] |
217 |
1 |
|
T25 |
9 |
|
T46 |
10 |
|
T41 |
1 |
| others[2] |
215 |
1 |
|
T8 |
1 |
|
T25 |
10 |
|
T46 |
7 |
| others[3] |
393 |
1 |
|
T23 |
1 |
|
T25 |
16 |
|
T46 |
20 |
| false |
122 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
6 |
| true |
5667 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T25 |
10 |
|
T46 |
9 |
|
T76 |
1 |
| others[1] |
215 |
1 |
|
T23 |
2 |
|
T8 |
1 |
|
T25 |
14 |
| others[2] |
219 |
1 |
|
T23 |
1 |
|
T25 |
9 |
|
T46 |
8 |
| others[3] |
368 |
1 |
|
T23 |
2 |
|
T25 |
13 |
|
T46 |
17 |
| false |
109 |
1 |
|
T23 |
1 |
|
T25 |
4 |
|
T46 |
4 |
| true |
5712 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T142 |
1 |
|
T193 |
1 |
|
T239 |
1 |
| others[1] |
1246 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T141 |
1 |
| others[2] |
1278 |
1 |
|
T296 |
1 |
|
T265 |
1 |
|
T262 |
1 |
| others[3] |
2047 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| false |
632 |
1 |
|
T297 |
1 |
|
T149 |
1 |
|
T346 |
1 |
| true |
428 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T179 |
1 |
|
T355 |
1 |
|
T356 |
1 |
| others[1] |
11 |
1 |
|
T12 |
1 |
|
T30 |
1 |
|
T166 |
1 |
| others[2] |
10 |
1 |
|
T92 |
1 |
|
T174 |
1 |
|
T357 |
1 |
| others[3] |
12 |
1 |
|
T172 |
1 |
|
T358 |
1 |
|
T359 |
1 |
| false |
7 |
1 |
|
T360 |
1 |
|
T361 |
1 |
|
T362 |
1 |
| true |
45 |
1 |
|
T14 |
1 |
|
T51 |
1 |
|
T52 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T363 |
1 |
|
T364 |
1 |
|
T365 |
1 |
| others[1] |
4 |
1 |
|
T336 |
1 |
|
T366 |
1 |
|
T367 |
1 |
| others[2] |
2 |
1 |
|
T220 |
1 |
|
T368 |
1 |
|
- |
- |
| others[3] |
3 |
1 |
|
T369 |
1 |
|
T370 |
1 |
|
T371 |
1 |
| false |
5 |
1 |
|
T221 |
1 |
|
T340 |
1 |
|
T196 |
1 |
| true |
30 |
1 |
|
T327 |
1 |
|
T301 |
1 |
|
T337 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |