Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9580 |
1 |
|
T147 |
1 |
|
T349 |
1 |
|
T317 |
1 |
| others[1] |
833 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T142 |
1 |
| others[2] |
759 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T146 |
1 |
| others[3] |
1307 |
1 |
|
T315 |
1 |
|
T144 |
1 |
|
T297 |
1 |
| false |
415 |
1 |
|
T140 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| true |
530 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2295 |
1 |
|
T5 |
16 |
|
T13 |
1 |
|
T6 |
10 |
| others[1] |
2278 |
1 |
|
T61 |
1 |
|
T139 |
1 |
|
T244 |
1 |
| others[2] |
2325 |
1 |
|
T140 |
1 |
|
T141 |
1 |
|
T142 |
1 |
| others[3] |
3743 |
1 |
|
T54 |
1 |
|
T143 |
1 |
|
T315 |
1 |
| false |
1224 |
1 |
|
T147 |
1 |
|
T241 |
1 |
|
T5 |
15 |
| true |
1559 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T23 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9026 |
1 |
|
T139 |
1 |
|
T296 |
1 |
|
T347 |
1 |
| others[1] |
262 |
1 |
|
T193 |
1 |
|
T241 |
1 |
|
T7 |
1 |
| others[2] |
290 |
1 |
|
T142 |
1 |
|
T297 |
1 |
|
T341 |
1 |
| others[3] |
469 |
1 |
|
T145 |
1 |
|
T149 |
1 |
|
T244 |
1 |
| false |
150 |
1 |
|
T147 |
1 |
|
T143 |
1 |
|
T316 |
1 |
| true |
3227 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T140 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9290 |
1 |
|
T54 |
1 |
|
T145 |
1 |
|
T1 |
1 |
| others[1] |
454 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T316 |
1 |
| others[2] |
470 |
1 |
|
T193 |
1 |
|
T341 |
1 |
|
T344 |
1 |
| others[3] |
755 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T296 |
1 |
| false |
246 |
1 |
|
T61 |
1 |
|
T6 |
4 |
|
T25 |
6 |
| true |
2209 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T142 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9023 |
1 |
|
T147 |
1 |
|
T193 |
1 |
|
T341 |
1 |
| others[1] |
261 |
1 |
|
T54 |
1 |
|
T315 |
1 |
|
T346 |
1 |
| others[2] |
267 |
1 |
|
T265 |
1 |
|
T262 |
1 |
|
T23 |
1 |
| others[3] |
442 |
1 |
|
T297 |
1 |
|
T145 |
1 |
|
T149 |
1 |
| false |
130 |
1 |
|
T144 |
1 |
|
T347 |
1 |
|
T25 |
2 |
| true |
3301 |
1 |
|
T61 |
1 |
|
T139 |
1 |
|
T140 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9010 |
1 |
|
T147 |
1 |
|
T297 |
1 |
|
T5 |
131 |
| others[1] |
244 |
1 |
|
T140 |
1 |
|
T265 |
1 |
|
T262 |
1 |
| others[2] |
252 |
1 |
|
T141 |
1 |
|
T25 |
8 |
|
T46 |
18 |
| others[3] |
450 |
1 |
|
T54 |
1 |
|
T143 |
1 |
|
T144 |
1 |
| false |
120 |
1 |
|
T142 |
1 |
|
T316 |
1 |
|
T347 |
1 |
| true |
3348 |
1 |
|
T61 |
1 |
|
T139 |
1 |
|
T193 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9589 |
1 |
|
T315 |
1 |
|
T149 |
1 |
|
T262 |
1 |
| others[1] |
779 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| others[2] |
809 |
1 |
|
T61 |
1 |
|
T142 |
1 |
|
T145 |
1 |
| others[3] |
1349 |
1 |
|
T141 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| false |
415 |
1 |
|
T147 |
1 |
|
T317 |
1 |
|
T1 |
1 |
| true |
483 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T23 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9577 |
1 |
|
T61 |
1 |
|
T142 |
1 |
|
T145 |
1 |
| others[1] |
823 |
1 |
|
T139 |
1 |
|
T146 |
1 |
|
T150 |
1 |
| others[2] |
775 |
1 |
|
T54 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| others[3] |
1284 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T315 |
1 |
| false |
402 |
1 |
|
T140 |
1 |
|
T241 |
1 |
|
T341 |
1 |
| true |
532 |
1 |
|
T1 |
2 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2276 |
1 |
|
T61 |
1 |
|
T142 |
1 |
|
T244 |
1 |
| others[1] |
2280 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T343 |
1 |
| others[2] |
2332 |
1 |
|
T140 |
1 |
|
T144 |
1 |
|
T145 |
1 |
| others[3] |
3773 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T143 |
1 |
| false |
1201 |
1 |
|
T193 |
1 |
|
T349 |
1 |
|
T341 |
1 |
| true |
1531 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9031 |
1 |
|
T142 |
1 |
|
T296 |
1 |
|
T241 |
1 |
| others[1] |
286 |
1 |
|
T349 |
1 |
|
T345 |
1 |
|
T23 |
2 |
| others[2] |
295 |
1 |
|
T145 |
1 |
|
T343 |
1 |
|
T347 |
1 |
| others[3] |
474 |
1 |
|
T61 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| false |
157 |
1 |
|
T147 |
1 |
|
T315 |
1 |
|
T146 |
1 |
| true |
3150 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T193 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9198 |
1 |
|
T139 |
1 |
|
T145 |
1 |
|
T146 |
1 |
| others[1] |
456 |
1 |
|
T143 |
1 |
|
T349 |
1 |
|
T347 |
1 |
| others[2] |
467 |
1 |
|
T54 |
1 |
|
T142 |
1 |
|
T344 |
1 |
| others[3] |
779 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T193 |
1 |
| false |
236 |
1 |
|
T316 |
1 |
|
T341 |
1 |
|
T1 |
1 |
| true |
2257 |
1 |
|
T61 |
1 |
|
T140 |
1 |
|
T315 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9035 |
1 |
|
T142 |
1 |
|
T146 |
1 |
|
T316 |
1 |
| others[1] |
243 |
1 |
|
T141 |
1 |
|
T150 |
1 |
|
T1 |
1 |
| others[2] |
264 |
1 |
|
T346 |
1 |
|
T23 |
3 |
|
T44 |
1 |
| others[3] |
440 |
1 |
|
T193 |
1 |
|
T143 |
1 |
|
T144 |
1 |
| false |
148 |
1 |
|
T315 |
1 |
|
T23 |
1 |
|
T25 |
5 |
| true |
3263 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9009 |
1 |
|
T61 |
1 |
|
T341 |
1 |
|
T347 |
1 |
| others[1] |
246 |
1 |
|
T315 |
1 |
|
T144 |
1 |
|
T296 |
1 |
| others[2] |
248 |
1 |
|
T142 |
1 |
|
T297 |
1 |
|
T265 |
1 |
| others[3] |
423 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T143 |
1 |
| false |
130 |
1 |
|
T149 |
1 |
|
T346 |
1 |
|
T25 |
6 |
| true |
3337 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T141 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9540 |
1 |
|
T193 |
1 |
|
T144 |
1 |
|
T239 |
1 |
| others[1] |
806 |
1 |
|
T139 |
1 |
|
T145 |
1 |
|
T241 |
1 |
| others[2] |
813 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T4 |
1 |
| others[3] |
1328 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T140 |
1 |
| false |
418 |
1 |
|
T315 |
1 |
|
T6 |
7 |
|
T25 |
5 |
| true |
488 |
1 |
|
T1 |
2 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9513 |
1 |
|
T142 |
1 |
|
T297 |
1 |
|
T146 |
1 |
| others[1] |
772 |
1 |
|
T61 |
1 |
|
T145 |
1 |
|
T344 |
1 |
| others[2] |
772 |
1 |
|
T54 |
1 |
|
T143 |
1 |
|
T315 |
1 |
| others[3] |
1349 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T193 |
1 |
| false |
454 |
1 |
|
T140 |
1 |
|
T141 |
1 |
|
T316 |
1 |
| true |
533 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2290 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T142 |
1 |
| others[1] |
2306 |
1 |
|
T140 |
1 |
|
T144 |
1 |
|
T296 |
1 |
| others[2] |
2274 |
1 |
|
T193 |
1 |
|
T297 |
1 |
|
T145 |
1 |
| others[3] |
3739 |
1 |
|
T54 |
1 |
|
T315 |
1 |
|
T239 |
1 |
| false |
1184 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T349 |
1 |
| true |
1600 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9022 |
1 |
|
T316 |
1 |
|
T5 |
131 |
|
T13 |
3 |
| others[1] |
284 |
1 |
|
T193 |
1 |
|
T144 |
1 |
|
T239 |
1 |
| others[2] |
283 |
1 |
|
T139 |
1 |
|
T149 |
1 |
|
T343 |
1 |
| others[3] |
436 |
1 |
|
T141 |
1 |
|
T142 |
1 |
|
T143 |
1 |
| false |
141 |
1 |
|
T147 |
1 |
|
T315 |
1 |
|
T349 |
1 |
| true |
3227 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T140 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9224 |
1 |
|
T139 |
1 |
|
T241 |
1 |
|
T150 |
1 |
| others[1] |
484 |
1 |
|
T61 |
1 |
|
T315 |
1 |
|
T146 |
1 |
| others[2] |
484 |
1 |
|
T54 |
1 |
|
T297 |
1 |
|
T349 |
1 |
| others[3] |
743 |
1 |
|
T141 |
1 |
|
T143 |
1 |
|
T239 |
1 |
| false |
261 |
1 |
|
T317 |
1 |
|
T6 |
6 |
|
T23 |
1 |
| true |
2197 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T142 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9009 |
1 |
|
T241 |
1 |
|
T346 |
1 |
|
T347 |
1 |
| others[1] |
285 |
1 |
|
T142 |
1 |
|
T150 |
1 |
|
T262 |
1 |
| others[2] |
278 |
1 |
|
T145 |
1 |
|
T239 |
1 |
|
T20 |
1 |
| others[3] |
425 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| false |
130 |
1 |
|
T1 |
1 |
|
T372 |
1 |
|
T25 |
6 |
| true |
3266 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T193 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8988 |
1 |
|
T296 |
1 |
|
T297 |
1 |
|
T146 |
1 |
| others[1] |
251 |
1 |
|
T149 |
1 |
|
T265 |
1 |
|
T23 |
1 |
| others[2] |
238 |
1 |
|
T61 |
1 |
|
T316 |
1 |
|
T22 |
1 |
| others[3] |
411 |
1 |
|
T139 |
1 |
|
T140 |
1 |
|
T143 |
1 |
| false |
134 |
1 |
|
T4 |
1 |
|
T372 |
1 |
|
T25 |
6 |
| true |
3371 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T141 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9520 |
1 |
|
T315 |
1 |
|
T145 |
1 |
|
T146 |
1 |
| others[1] |
798 |
1 |
|
T139 |
1 |
|
T142 |
1 |
|
T297 |
1 |
| others[2] |
782 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T141 |
1 |
| others[3] |
1354 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T193 |
1 |
| false |
440 |
1 |
|
T239 |
1 |
|
T241 |
1 |
|
T244 |
1 |
| true |
499 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T23 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9523 |
1 |
|
T142 |
1 |
|
T296 |
1 |
|
T241 |
1 |
| others[1] |
804 |
1 |
|
T54 |
1 |
|
T143 |
1 |
|
T144 |
1 |
| others[2] |
778 |
1 |
|
T61 |
1 |
|
T141 |
1 |
|
T297 |
1 |
| others[3] |
1340 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T193 |
1 |
| false |
428 |
1 |
|
T139 |
1 |
|
T315 |
1 |
|
T244 |
1 |
| true |
520 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2290 |
1 |
|
T345 |
1 |
|
T5 |
24 |
|
T13 |
1 |
| others[1] |
2183 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| others[2] |
2246 |
1 |
|
T144 |
1 |
|
T146 |
1 |
|
T341 |
1 |
| others[3] |
3864 |
1 |
|
T61 |
1 |
|
T142 |
1 |
|
T193 |
1 |
| false |
1246 |
1 |
|
T147 |
1 |
|
T145 |
1 |
|
T241 |
1 |
| true |
1564 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9013 |
1 |
|
T142 |
1 |
|
T149 |
1 |
|
T317 |
1 |
| others[1] |
254 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T349 |
1 |
| others[2] |
290 |
1 |
|
T141 |
1 |
|
T296 |
1 |
|
T316 |
1 |
| others[3] |
505 |
1 |
|
T61 |
1 |
|
T144 |
1 |
|
T345 |
1 |
| false |
158 |
1 |
|
T239 |
1 |
|
T7 |
1 |
|
T23 |
1 |
| true |
3173 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T193 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9192 |
1 |
|
T265 |
1 |
|
T346 |
1 |
|
T5 |
131 |
| others[1] |
461 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T6 |
6 |
| others[2] |
467 |
1 |
|
T61 |
1 |
|
T193 |
1 |
|
T146 |
1 |
| others[3] |
729 |
1 |
|
T244 |
1 |
|
T344 |
1 |
|
T1 |
1 |
| false |
250 |
1 |
|
T345 |
1 |
|
T6 |
2 |
|
T25 |
4 |
| true |
2294 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T139 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9013 |
1 |
|
T315 |
1 |
|
T296 |
1 |
|
T4 |
1 |
| others[1] |
266 |
1 |
|
T343 |
1 |
|
T1 |
1 |
|
T25 |
12 |
| others[2] |
265 |
1 |
|
T140 |
1 |
|
T193 |
1 |
|
T239 |
1 |
| others[3] |
438 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T139 |
1 |
| false |
131 |
1 |
|
T244 |
1 |
|
T27 |
1 |
|
T25 |
7 |
| true |
3280 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T142 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9011 |
1 |
|
T144 |
1 |
|
T349 |
1 |
|
T5 |
131 |
| others[1] |
275 |
1 |
|
T140 |
1 |
|
T297 |
1 |
|
T344 |
1 |
| others[2] |
222 |
1 |
|
T147 |
1 |
|
T244 |
1 |
|
T343 |
1 |
| others[3] |
414 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T193 |
1 |
| false |
121 |
1 |
|
T145 |
1 |
|
T239 |
1 |
|
T317 |
1 |
| true |
3350 |
1 |
|
T61 |
1 |
|
T139 |
1 |
|
T142 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9541 |
1 |
|
T193 |
1 |
|
T296 |
1 |
|
T146 |
1 |
| others[1] |
780 |
1 |
|
T61 |
1 |
|
T141 |
1 |
|
T145 |
1 |
| others[2] |
807 |
1 |
|
T139 |
1 |
|
T315 |
1 |
|
T297 |
1 |
| others[3] |
1359 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T142 |
1 |
| false |
417 |
1 |
|
T140 |
1 |
|
T341 |
1 |
|
T345 |
1 |
| true |
489 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T23 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9565 |
1 |
|
T297 |
1 |
|
T145 |
1 |
|
T146 |
1 |
| others[1] |
812 |
1 |
|
T139 |
1 |
|
T142 |
1 |
|
T315 |
1 |
| others[2] |
790 |
1 |
|
T54 |
1 |
|
T296 |
1 |
|
T239 |
1 |
| others[3] |
1308 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T140 |
1 |
| false |
407 |
1 |
|
T141 |
1 |
|
T193 |
1 |
|
T346 |
1 |
| true |
511 |
1 |
|
T1 |
2 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2275 |
1 |
|
T61 |
1 |
|
T141 |
1 |
|
T142 |
1 |
| others[1] |
2336 |
1 |
|
T54 |
1 |
|
T315 |
1 |
|
T144 |
1 |
| others[2] |
2294 |
1 |
|
T140 |
1 |
|
T143 |
1 |
|
T296 |
1 |
| others[3] |
3761 |
1 |
|
T147 |
1 |
|
T193 |
1 |
|
T316 |
1 |
| false |
1169 |
1 |
|
T139 |
1 |
|
T241 |
1 |
|
T265 |
1 |
| true |
1558 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9026 |
1 |
|
T147 |
1 |
|
T143 |
1 |
|
T5 |
131 |
| others[1] |
277 |
1 |
|
T316 |
1 |
|
T22 |
1 |
|
T23 |
1 |
| others[2] |
280 |
1 |
|
T141 |
1 |
|
T296 |
1 |
|
T145 |
1 |
| others[3] |
465 |
1 |
|
T142 |
1 |
|
T146 |
1 |
|
T241 |
1 |
| false |
143 |
1 |
|
T144 |
1 |
|
T343 |
1 |
|
T1 |
1 |
| true |
3202 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T139 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |