Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9219 |
1 |
|
T139 |
1 |
|
T142 |
1 |
|
T143 |
1 |
| others[1] |
506 |
1 |
|
T297 |
1 |
|
T343 |
1 |
|
T6 |
2 |
| others[2] |
451 |
1 |
|
T296 |
1 |
|
T344 |
1 |
|
T347 |
1 |
| others[3] |
773 |
1 |
|
T315 |
1 |
|
T316 |
1 |
|
T265 |
1 |
| false |
244 |
1 |
|
T144 |
1 |
|
T6 |
4 |
|
T23 |
4 |
| true |
2200 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9030 |
1 |
|
T147 |
1 |
|
T4 |
1 |
|
T5 |
131 |
| others[1] |
277 |
1 |
|
T54 |
1 |
|
T315 |
1 |
|
T146 |
1 |
| others[2] |
260 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T296 |
1 |
| others[3] |
431 |
1 |
|
T297 |
1 |
|
T349 |
1 |
|
T346 |
1 |
| false |
155 |
1 |
|
T23 |
1 |
|
T190 |
1 |
|
T25 |
6 |
| true |
3240 |
1 |
|
T61 |
1 |
|
T140 |
1 |
|
T142 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9025 |
1 |
|
T145 |
1 |
|
T149 |
1 |
|
T349 |
1 |
| others[1] |
235 |
1 |
|
T142 |
1 |
|
T343 |
1 |
|
T23 |
2 |
| others[2] |
262 |
1 |
|
T61 |
1 |
|
T344 |
1 |
|
T1 |
1 |
| others[3] |
420 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T144 |
1 |
| false |
133 |
1 |
|
T25 |
5 |
|
T46 |
7 |
|
T373 |
1 |
| true |
3318 |
1 |
|
T139 |
1 |
|
T140 |
1 |
|
T141 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9537 |
1 |
|
T149 |
1 |
|
T244 |
1 |
|
T265 |
1 |
| others[1] |
809 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T296 |
1 |
| others[2] |
826 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T141 |
1 |
| others[3] |
1293 |
1 |
|
T140 |
1 |
|
T193 |
1 |
|
T144 |
1 |
| false |
418 |
1 |
|
T6 |
3 |
|
T25 |
9 |
|
T46 |
11 |
| true |
510 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T23 |
7 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9523 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T193 |
1 |
| others[1] |
792 |
1 |
|
T141 |
1 |
|
T239 |
1 |
|
T241 |
1 |
| others[2] |
787 |
1 |
|
T139 |
1 |
|
T315 |
1 |
|
T144 |
1 |
| others[3] |
1340 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T143 |
1 |
| false |
435 |
1 |
|
T142 |
1 |
|
T6 |
2 |
|
T25 |
13 |
| true |
516 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2293 |
1 |
|
T147 |
1 |
|
T145 |
1 |
|
T149 |
1 |
| others[1] |
2221 |
1 |
|
T140 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| others[2] |
2309 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T20 |
1 |
| others[3] |
3797 |
1 |
|
T139 |
1 |
|
T142 |
1 |
|
T315 |
1 |
| false |
1236 |
1 |
|
T61 |
1 |
|
T347 |
1 |
|
T5 |
13 |
| true |
1537 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9030 |
1 |
|
T144 |
1 |
|
T5 |
131 |
|
T13 |
3 |
| others[1] |
274 |
1 |
|
T142 |
1 |
|
T146 |
1 |
|
T262 |
1 |
| others[2] |
271 |
1 |
|
T139 |
1 |
|
T143 |
1 |
|
T25 |
4 |
| others[3] |
442 |
1 |
|
T54 |
1 |
|
T193 |
1 |
|
T239 |
1 |
| false |
162 |
1 |
|
T315 |
1 |
|
T316 |
1 |
|
T20 |
1 |
| true |
3214 |
1 |
|
T61 |
1 |
|
T147 |
1 |
|
T140 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9198 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T141 |
1 |
| others[1] |
512 |
1 |
|
T296 |
1 |
|
T145 |
1 |
|
T149 |
1 |
| others[2] |
504 |
1 |
|
T341 |
1 |
|
T22 |
1 |
|
T6 |
9 |
| others[3] |
785 |
1 |
|
T315 |
1 |
|
T316 |
1 |
|
T150 |
1 |
| false |
246 |
1 |
|
T6 |
1 |
|
T8 |
1 |
|
T25 |
9 |
| true |
2148 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T140 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9030 |
1 |
|
T61 |
1 |
|
T140 |
1 |
|
T142 |
1 |
| others[1] |
247 |
1 |
|
T241 |
1 |
|
T25 |
10 |
|
T46 |
9 |
| others[2] |
264 |
1 |
|
T345 |
1 |
|
T262 |
1 |
|
T25 |
12 |
| others[3] |
431 |
1 |
|
T139 |
1 |
|
T239 |
1 |
|
T244 |
1 |
| false |
121 |
1 |
|
T149 |
1 |
|
T316 |
1 |
|
T4 |
1 |
| true |
3300 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T141 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9002 |
1 |
|
T141 |
1 |
|
T146 |
1 |
|
T262 |
1 |
| others[1] |
262 |
1 |
|
T315 |
1 |
|
T297 |
1 |
|
T150 |
1 |
| others[2] |
269 |
1 |
|
T142 |
1 |
|
T341 |
1 |
|
T345 |
1 |
| others[3] |
452 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T139 |
1 |
| false |
107 |
1 |
|
T145 |
1 |
|
T239 |
1 |
|
T265 |
1 |
| true |
3301 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T193 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9527 |
1 |
|
T61 |
1 |
|
T1 |
1 |
|
T5 |
131 |
| others[1] |
830 |
1 |
|
T140 |
1 |
|
T141 |
1 |
|
T142 |
1 |
| others[2] |
795 |
1 |
|
T147 |
1 |
|
T143 |
1 |
|
T315 |
1 |
| others[3] |
1329 |
1 |
|
T54 |
1 |
|
T193 |
1 |
|
T296 |
1 |
| false |
414 |
1 |
|
T139 |
1 |
|
T144 |
1 |
|
T239 |
1 |
| true |
498 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9524 |
1 |
|
T142 |
1 |
|
T143 |
1 |
|
T145 |
1 |
| others[1] |
794 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T193 |
1 |
| others[2] |
800 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T144 |
1 |
| others[3] |
1328 |
1 |
|
T61 |
1 |
|
T140 |
1 |
|
T146 |
1 |
| false |
440 |
1 |
|
T315 |
1 |
|
T316 |
1 |
|
T345 |
1 |
| true |
507 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2198 |
1 |
|
T144 |
1 |
|
T145 |
1 |
|
T239 |
1 |
| others[1] |
2310 |
1 |
|
T54 |
1 |
|
T140 |
1 |
|
T143 |
1 |
| others[2] |
2267 |
1 |
|
T61 |
1 |
|
T316 |
1 |
|
T344 |
1 |
| others[3] |
3840 |
1 |
|
T147 |
1 |
|
T139 |
1 |
|
T141 |
1 |
| false |
1172 |
1 |
|
T142 |
1 |
|
T297 |
1 |
|
T146 |
1 |
| true |
1606 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9001 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T296 |
1 |
| others[1] |
284 |
1 |
|
T61 |
1 |
|
T143 |
1 |
|
T144 |
1 |
| others[2] |
270 |
1 |
|
T149 |
1 |
|
T346 |
1 |
|
T7 |
1 |
| others[3] |
465 |
1 |
|
T139 |
1 |
|
T142 |
1 |
|
T145 |
1 |
| false |
150 |
1 |
|
T193 |
1 |
|
T150 |
1 |
|
T1 |
1 |
| true |
3223 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T315 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9197 |
1 |
|
T262 |
1 |
|
T1 |
1 |
|
T4 |
1 |
| others[1] |
528 |
1 |
|
T140 |
1 |
|
T297 |
1 |
|
T145 |
1 |
| others[2] |
436 |
1 |
|
T239 |
1 |
|
T345 |
1 |
|
T346 |
1 |
| others[3] |
829 |
1 |
|
T141 |
1 |
|
T146 |
1 |
|
T241 |
1 |
| false |
219 |
1 |
|
T316 |
1 |
|
T1 |
1 |
|
T6 |
2 |
| true |
2184 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9012 |
1 |
|
T241 |
1 |
|
T5 |
131 |
|
T13 |
3 |
| others[1] |
275 |
1 |
|
T61 |
1 |
|
T296 |
1 |
|
T1 |
1 |
| others[2] |
260 |
1 |
|
T142 |
1 |
|
T193 |
1 |
|
T297 |
1 |
| others[3] |
413 |
1 |
|
T140 |
1 |
|
T143 |
1 |
|
T345 |
1 |
| false |
147 |
1 |
|
T139 |
1 |
|
T149 |
1 |
|
T150 |
1 |
| true |
3286 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T141 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8998 |
1 |
|
T1 |
1 |
|
T5 |
131 |
|
T13 |
3 |
| others[1] |
270 |
1 |
|
T297 |
1 |
|
T149 |
1 |
|
T150 |
1 |
| others[2] |
265 |
1 |
|
T142 |
1 |
|
T317 |
1 |
|
T25 |
10 |
| others[3] |
428 |
1 |
|
T141 |
1 |
|
T144 |
1 |
|
T145 |
1 |
| false |
140 |
1 |
|
T372 |
1 |
|
T25 |
6 |
|
T46 |
7 |
| true |
3292 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T147 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9542 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T146 |
1 |
| others[1] |
793 |
1 |
|
T143 |
1 |
|
T144 |
1 |
|
T297 |
1 |
| others[2] |
783 |
1 |
|
T139 |
1 |
|
T140 |
1 |
|
T142 |
1 |
| others[3] |
1358 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T296 |
1 |
| false |
423 |
1 |
|
T315 |
1 |
|
T341 |
1 |
|
T22 |
1 |
| true |
494 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9576 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T140 |
1 |
| others[1] |
812 |
1 |
|
T61 |
1 |
|
T193 |
1 |
|
T143 |
1 |
| others[2] |
810 |
1 |
|
T147 |
1 |
|
T141 |
1 |
|
T142 |
1 |
| others[3] |
1248 |
1 |
|
T296 |
1 |
|
T145 |
1 |
|
T146 |
1 |
| false |
422 |
1 |
|
T239 |
1 |
|
T6 |
5 |
|
T190 |
1 |
| true |
525 |
1 |
|
T1 |
2 |
|
T12 |
1 |
|
T49 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2284 |
1 |
|
T139 |
1 |
|
T141 |
1 |
|
T144 |
1 |
| others[1] |
2213 |
1 |
|
T140 |
1 |
|
T193 |
1 |
|
T315 |
1 |
| others[2] |
2312 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T142 |
1 |
| others[3] |
3886 |
1 |
|
T61 |
1 |
|
T146 |
1 |
|
T241 |
1 |
| false |
1176 |
1 |
|
T5 |
10 |
|
T13 |
2 |
|
T6 |
4 |
| true |
1522 |
1 |
|
T12 |
1 |
|
T49 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9025 |
1 |
|
T316 |
1 |
|
T341 |
1 |
|
T345 |
1 |
| others[1] |
279 |
1 |
|
T61 |
1 |
|
T145 |
1 |
|
T343 |
1 |
| others[2] |
282 |
1 |
|
T150 |
1 |
|
T23 |
1 |
|
T44 |
1 |
| others[3] |
452 |
1 |
|
T141 |
1 |
|
T296 |
1 |
|
T344 |
1 |
| false |
143 |
1 |
|
T297 |
1 |
|
T346 |
1 |
|
T25 |
3 |
| true |
3212 |
1 |
|
T54 |
1 |
|
T147 |
1 |
|
T139 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9245 |
1 |
|
T147 |
1 |
|
T143 |
1 |
|
T343 |
1 |
| others[1] |
498 |
1 |
|
T193 |
1 |
|
T146 |
1 |
|
T265 |
1 |
| others[2] |
439 |
1 |
|
T139 |
1 |
|
T140 |
1 |
|
T239 |
1 |
| others[3] |
753 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T142 |
1 |
| false |
251 |
1 |
|
T341 |
1 |
|
T6 |
3 |
|
T7 |
1 |
| true |
2207 |
1 |
|
T141 |
1 |
|
T315 |
1 |
|
T144 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9001 |
1 |
|
T54 |
1 |
|
T61 |
1 |
|
T142 |
1 |
| others[1] |
268 |
1 |
|
T144 |
1 |
|
T349 |
1 |
|
T317 |
1 |
| others[2] |
300 |
1 |
|
T146 |
1 |
|
T44 |
1 |
|
T372 |
1 |
| others[3] |
406 |
1 |
|
T315 |
1 |
|
T241 |
1 |
|
T316 |
1 |
| false |
140 |
1 |
|
T139 |
1 |
|
T25 |
8 |
|
T46 |
7 |
| true |
3278 |
1 |
|
T147 |
1 |
|
T140 |
1 |
|
T141 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9009 |
1 |
|
T147 |
1 |
|
T5 |
131 |
|
T13 |
3 |
| others[1] |
243 |
1 |
|
T315 |
1 |
|
T296 |
1 |
|
T239 |
1 |
| others[2] |
229 |
1 |
|
T61 |
1 |
|
T141 |
1 |
|
T297 |
1 |
| others[3] |
388 |
1 |
|
T142 |
1 |
|
T193 |
1 |
|
T241 |
1 |
| false |
134 |
1 |
|
T144 |
1 |
|
T1 |
1 |
|
T44 |
1 |
| true |
3390 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T140 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9548 |
1 |
|
T141 |
1 |
|
T144 |
1 |
|
T239 |
1 |
| others[1] |
757 |
1 |
|
T147 |
1 |
|
T142 |
1 |
|
T146 |
1 |
| others[2] |
819 |
1 |
|
T139 |
1 |
|
T297 |
1 |
|
T316 |
1 |
| others[3] |
1351 |
1 |
|
T61 |
1 |
|
T140 |
1 |
|
T193 |
1 |
| false |
412 |
1 |
|
T54 |
1 |
|
T241 |
1 |
|
T317 |
1 |
| true |
506 |
1 |
|
T1 |
1 |
|
T12 |
1 |
|
T49 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |