Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	222655	1		T1	4		T2	340		T4	695
auto[FlashEraseBank]	236386	1		T1	4		T4	561		T12	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	252937	1		T1	4		T2	9		T5	392
auto[FlashOpProgram]	187370	1		T1	4		T2	320		T4	1256
auto[FlashOpErase]	14734	1		T2	11		T5	195		T13	10
auto[FlashOpInvalid]	4000	1		T116	200		T126	200		T268	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	252937	1		T1	4		T2	9		T5	392
op[FlashOpProgram]	187370	1		T1	4		T2	320		T4	1256
op[FlashOpErase]	14734	1		T2	11		T5	195		T13	10
read_erase_read	755	1		T23	1		T25	7		T46	4
read_prog_read	1371	1		T1	1		T23	2		T25	7

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	323381	1		T1	8		T4	1043		T13	390
auto[FlashPartInfo]	132462	1		T2	340		T4	213		T5	782
auto[FlashPartInfo1]	853	1		T7	4		T8	1		T27	4
auto[FlashPartInfo2]	2345	1		T7	3		T8	5		T27	9

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	192425	1		T1	4		T13	258		T6	47
auto[FlashPartData]	auto[FlashOpProgram]	123376	1		T1	4		T4	1043		T13	128
auto[FlashPartData]	auto[FlashOpErase]	3672	1		T13	4		T23	2		T25	39
auto[FlashPartData]	auto[FlashOpInvalid]	3908	1		T116	192		T126	192		T268	200
auto[FlashPartInfo]	auto[FlashOpRead]	58376	1		T2	9		T5	392		T12	1
auto[FlashPartInfo]	auto[FlashOpProgram]	62955	1		T2	320		T4	213		T5	195
auto[FlashPartInfo]	auto[FlashOpErase]	11051	1		T2	11		T5	195		T13	6
auto[FlashPartInfo]	auto[FlashOpInvalid]	80	1		T116	6		T126	6		T374	6
auto[FlashPartInfo1]	auto[FlashOpRead]	712	1		T7	4		T8	1		T27	4
auto[FlashPartInfo1]	auto[FlashOpProgram]	135	1		T229	2		T129	32		T103	1
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T103	1		T375	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T103	2		T375	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1424	1		T7	3		T8	5		T27	9
auto[FlashPartInfo2]	auto[FlashOpProgram]	904	1		T65	33		T115	10		T123	2
auto[FlashPartInfo2]	auto[FlashOpErase]	9	1		T116	1		T126	1		T102	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T116	2		T126	2		T376	4