Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.95	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	8	24	75.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	8	24	75.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28452	1		T5	388		T13	8		T31	768
auto[1]	10	1		T200	1		T186	1		T298	4
auto[2]	208	1		T299	23		T209	13		T200	6
auto[3]	270	1		T207	91		T107	28		T72	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7253	1		T5	97		T13	2		T31	192
evic_idx[1]	7246	1		T5	97		T13	2		T31	192
evic_idx[2]	7228	1		T5	97		T13	2		T31	192
evic_idx[3]	7213	1		T5	97		T13	2		T31	192

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	27838	1		T5	388		T13	4		T31	768
evic_op[2]	510	1		T122	32		T72	1		T299	23

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	8	24	75.00	8

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[1] - auto[2]]	--	--	8

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6906	1		T5	97		T13	1		T31	192
evic_idx[0]	evic_op[1]	auto[3]	64	1		T207	31		T107	6		T300	13
evic_idx[0]	evic_op[2]	auto[0]	69	1		T122	8		T301	1		T97	1
evic_idx[0]	evic_op[2]	auto[1]	2	1		T298	1		T302	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	49	1		T299	10		T209	4		T200	1
evic_idx[0]	evic_op[2]	auto[3]	15	1		T73	1		T303	1		T304	1
evic_idx[1]	evic_op[1]	auto[0]	6901	1		T5	97		T13	1		T31	192
evic_idx[1]	evic_op[1]	auto[3]	69	1		T207	27		T107	8		T300	15
evic_idx[1]	evic_op[2]	auto[0]	68	1		T122	8		T301	1		T270	10
evic_idx[1]	evic_op[2]	auto[1]	4	1		T200	1		T186	1		T298	1
evic_idx[1]	evic_op[2]	auto[2]	44	1		T299	3		T209	5		T305	11
evic_idx[1]	evic_op[2]	auto[3]	12	1		T306	1		T307	1		T308	1
evic_idx[2]	evic_op[1]	auto[0]	6902	1		T5	97		T13	1		T31	192
evic_idx[2]	evic_op[1]	auto[3]	56	1		T207	20		T107	9		T300	14
evic_idx[2]	evic_op[2]	auto[0]	66	1		T122	8		T301	1		T270	10
evic_idx[2]	evic_op[2]	auto[1]	2	1		T298	1		T302	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	48	1		T299	2		T209	4		T200	1
evic_idx[2]	evic_op[2]	auto[3]	6	1		T306	1		T309	1		T310	1
evic_idx[3]	evic_op[1]	auto[0]	6901	1		T5	97		T13	1		T31	192
evic_idx[3]	evic_op[1]	auto[3]	39	1		T207	13		T107	5		T300	7
evic_idx[3]	evic_op[2]	auto[0]	67	1		T122	8		T301	1		T270	10
evic_idx[3]	evic_op[2]	auto[1]	2	1		T298	1		T302	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	47	1		T299	8		T200	4		T305	8
evic_idx[3]	evic_op[2]	auto[3]	9	1		T72	1		T311	1		T312	1