Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	62437	1		T4	7307		T66	3234		T67	6821
prog_lvl[2]	4064	1		T66	1		T377	699		T378	1
prog_lvl[3]	5	1		T377	1		T379	1		T380	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	6133	1		T48	15		T71	1040		T69	14
rd_lvl[2]	19872	1		T48	524		T71	1001		T215	515
rd_lvl[3]	17622	1		T48	15		T215	832		T381	552
rd_lvl[4]	22186	1		T48	11		T382	2781		T381	1
rd_lvl[5]	11946	1		T48	2		T382	639		T383	1471
rd_lvl[6]	9685	1		T48	478		T383	959		T215	84
rd_lvl[7]	9419	1		T48	1310		T384	1068		T385	699
rd_lvl[8]	6429	1		T48	488		T384	636		T216	475
rd_lvl[9]	5778	1		T386	485		T387	17		T216	747
rd_lvl[10]	6052	1		T388	388		T386	400		T202	75
rd_lvl[11]	4688	1		T48	18		T388	302		T389	439
rd_lvl[12]	4456	1		T390	544		T389	306		T216	78
rd_lvl[13]	4341	1		T44	489		T272	504		T390	484
rd_lvl[14]	5058	1		T44	221		T272	391		T391	692
rd_lvl[15]	5293	1		T69	382		T70	631		T208	441