Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	342675	1		T54	5		T61	5		T147	5
all_pins[1]	342675	1		T54	5		T61	5		T147	5
all_pins[2]	342675	1		T54	5		T61	5		T147	5
all_pins[3]	342675	1		T54	5		T61	5		T147	5
all_pins[4]	342675	1		T54	5		T61	5		T147	5
all_pins[5]	342675	1		T54	5		T61	5		T147	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1663075	1		T54	19		T61	24		T147	27
values[0x1]	392975	1		T54	11		T61	6		T147	3
transitions[0x0=>0x1]	370748	1		T54	8		T61	4		T147	3
transitions[0x1=>0x0]	370755	1		T54	8		T61	5		T147	3

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	282732	1		T54	4		T61	3		T147	4
all_pins[0]	values[0x1]	59943	1		T54	1		T61	2		T147	1
all_pins[0]	transitions[0x0=>0x1]	59931	1		T61	2		T147	1		T193	1
all_pins[0]	transitions[0x1=>0x0]	75535	1		T54	3		T315	2		T296	1
all_pins[1]	values[0x0]	267128	1		T54	1		T61	5		T147	5
all_pins[1]	values[0x1]	75547	1		T54	4		T315	2		T296	1
all_pins[1]	transitions[0x0=>0x1]	75533	1		T54	3		T315	2		T296	1
all_pins[1]	transitions[0x1=>0x0]	13598	1		T61	1		T193	1		T297	2
all_pins[2]	values[0x0]	329063	1		T54	4		T61	4		T147	5
all_pins[2]	values[0x1]	13612	1		T54	1		T61	1		T193	1
all_pins[2]	transitions[0x0=>0x1]	10502	1		T54	1		T61	1		T193	1
all_pins[2]	transitions[0x1=>0x0]	140160	1		T54	2		T193	3		T296	3
all_pins[3]	values[0x0]	199405	1		T54	3		T61	5		T147	5
all_pins[3]	values[0x1]	143270	1		T54	2		T193	3		T296	3
all_pins[3]	transitions[0x0=>0x1]	124219	1		T54	2		T193	3		T296	2
all_pins[3]	transitions[0x1=>0x0]	81478	1		T61	1		T193	1		T315	2
all_pins[4]	values[0x0]	242146	1		T54	5		T61	4		T147	5
all_pins[4]	values[0x1]	100529	1		T61	1		T193	1		T315	2
all_pins[4]	transitions[0x0=>0x1]	100509	1		T315	2		T296	1		T297	1
all_pins[4]	transitions[0x1=>0x0]	54	1		T54	3		T61	1		T147	2
all_pins[5]	values[0x0]	342601	1		T54	2		T61	3		T147	3
all_pins[5]	values[0x1]	74	1		T54	3		T61	2		T147	2
all_pins[5]	transitions[0x0=>0x1]	54	1		T54	2		T61	1		T147	2
all_pins[5]	transitions[0x1=>0x0]	59930	1		T61	2		T147	1		T193	1