Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T54	4		T61	4		T147	4
all_values[1]	281	1		T54	4		T61	4		T147	4
all_values[2]	281	1		T54	4		T61	4		T147	4
all_values[3]	281	1		T54	4		T61	4		T147	4
all_values[4]	281	1		T54	4		T61	4		T147	4
all_values[5]	281	1		T54	4		T61	4		T147	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	908	1		T54	11		T61	14		T147	12
auto[1]	778	1		T54	13		T61	10		T147	12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	693	1		T54	4		T61	9		T147	9
auto[1]	993	1		T54	20		T61	15		T147	15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1001	1		T54	12		T61	13		T147	11
auto[1]	685	1		T54	12		T61	11		T147	13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	55	1		T61	2		T193	1		T315	2
all_values[0]	auto[0]	auto[0]	auto[1]	27	1		T54	1		T193	3		T239	1
all_values[0]	auto[0]	auto[1]	auto[0]	68	1		T147	1		T193	1		T315	2
all_values[0]	auto[0]	auto[1]	auto[1]	24	1		T61	1		T147	1		T296	1
all_values[0]	auto[1]	auto[0]	auto[1]	51	1		T54	1		T61	1		T147	1
all_values[0]	auto[1]	auto[1]	auto[1]	56	1		T54	2		T147	1		T193	2
all_values[1]	auto[0]	auto[0]	auto[0]	75	1		T61	1		T147	1		T193	1
all_values[1]	auto[0]	auto[0]	auto[1]	22	1		T193	1		T315	1		T296	1
all_values[1]	auto[0]	auto[1]	auto[0]	61	1		T61	1		T147	1		T193	2
all_values[1]	auto[0]	auto[1]	auto[1]	21	1		T54	2		T315	1		T241	1
all_values[1]	auto[1]	auto[0]	auto[1]	60	1		T54	1		T61	2		T193	3
all_values[1]	auto[1]	auto[1]	auto[1]	42	1		T54	1		T147	2		T296	1
all_values[2]	auto[0]	auto[0]	auto[0]	64	1		T61	1		T193	2		T315	3
all_values[2]	auto[0]	auto[0]	auto[1]	27	1		T54	1		T297	1		T317	2
all_values[2]	auto[0]	auto[1]	auto[0]	47	1		T61	1		T147	1		T193	2
all_values[2]	auto[0]	auto[1]	auto[1]	29	1		T54	1		T193	1		T239	2
all_values[2]	auto[1]	auto[0]	auto[1]	64	1		T54	1		T147	2		T193	2
all_values[2]	auto[1]	auto[1]	auto[1]	50	1		T54	1		T61	2		T147	1
all_values[3]	auto[0]	auto[0]	auto[0]	64	1		T54	2		T61	1		T147	2
all_values[3]	auto[0]	auto[0]	auto[1]	18	1		T61	1		T296	1		T316	2
all_values[3]	auto[0]	auto[1]	auto[0]	54	1		T193	2		T315	2		T297	2
all_values[3]	auto[0]	auto[1]	auto[1]	33	1		T54	1		T193	1		T296	2
all_values[3]	auto[1]	auto[0]	auto[1]	59	1		T54	1		T61	2		T147	2
all_values[3]	auto[1]	auto[1]	auto[1]	53	1		T193	2		T296	2		T239	4
all_values[4]	auto[0]	auto[0]	auto[0]	63	1		T54	1		T61	1		T147	2
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T54	1		T315	1		T241	1
all_values[4]	auto[0]	auto[1]	auto[0]	41	1		T54	1		T147	1		T193	1
all_values[4]	auto[0]	auto[1]	auto[1]	21	1		T61	1		T315	1		T297	1
all_values[4]	auto[1]	auto[0]	auto[1]	83	1		T61	1		T147	1		T193	2
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T54	1		T61	1		T193	1
all_values[5]	auto[0]	auto[0]	auto[0]	56	1		T193	1		T315	1		T296	4
all_values[5]	auto[0]	auto[0]	auto[1]	28	1		T193	1		T315	1		T296	1
all_values[5]	auto[0]	auto[1]	auto[0]	45	1		T61	1		T315	1		T296	1
all_values[5]	auto[0]	auto[1]	auto[1]	30	1		T54	1		T61	1		T147	1
all_values[5]	auto[1]	auto[0]	auto[1]	64	1		T54	1		T61	1		T147	1
all_values[5]	auto[1]	auto[1]	auto[1]	58	1		T54	2		T61	1		T147	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal