Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23426576	1		T17	14		T54	76		T55	56
full_word	7453263	1		T17	1		T54	48		T55	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	30879519	1		T17	15		T54	124		T55	57
auto[TlIntgErrCmd]	100	1		T57	6		T58	4		T243	2
auto[TlIntgErrData]	108	1		T57	11		T58	8		T243	4
auto[TlIntgErrBoth]	112	1		T57	3		T58	8		T243	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26604791	1		T17	15		T54	68		T55	57
auto[1]	4275048	1		T54	56		T56	318		T59	103

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22811233	1		T17	14		T54	64		T55	56
auto[TlIntgErrNone]	partial	auto[1]	615045	1		T54	12		T56	135		T59	42
auto[TlIntgErrNone]	full_word	auto[0]	3793416	1		T17	1		T54	4		T55	1
auto[TlIntgErrNone]	full_word	auto[1]	3659825	1		T54	44		T56	183		T59	61
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T57	3		T58	1		T243	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T57	3		T58	3		T243	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T319	1		T321	1		T318	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T324	1		T325	3		-	-
auto[TlIntgErrData]	partial	auto[0]	49	1		T57	5		T58	3		T243	3
auto[TlIntgErrData]	partial	auto[1]	53	1		T57	6		T58	5		T243	1
auto[TlIntgErrData]	full_word	auto[0]	3	1		T319	1		T321	1		T293	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T319	1		T293	1		T326	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1		T57	2		T58	4		T243	2
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T57	1		T58	4		T243	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T319	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T319	1		T321	1		T322	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21210	1		T56	422		T57	18		T58	18
full_word	4340021	1		T56	77		T57	1		T58	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4360926	1		T56	499		T139	1130		T140	1566
auto[TlIntgErrCmd]	103	1		T57	1		T58	5		T243	3
auto[TlIntgErrData]	103	1		T57	8		T58	8		T243	3
auto[TlIntgErrBoth]	99	1		T57	10		T58	6		T243	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4335441	1		T56	4		T57	6		T58	8
auto[1]	25790	1		T56	495		T57	13		T58	11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1283	1		T56	3		T139	38		T140	86
auto[TlIntgErrNone]	partial	auto[1]	19642	1		T56	419		T139	781		T140	1068
auto[TlIntgErrNone]	full_word	auto[0]	4334030	1		T56	1		T139	3		T140	11
auto[TlIntgErrNone]	full_word	auto[1]	5971	1		T56	76		T139	308		T140	401
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T58	2		T243	1		T245	2
auto[TlIntgErrCmd]	partial	auto[1]	64	1		T57	1		T58	3		T243	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T245	1		T321	1		T261	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T261	1		T293	1		-	-
auto[TlIntgErrData]	partial	auto[0]	54	1		T57	5		T58	5		T243	1
auto[TlIntgErrData]	partial	auto[1]	42	1		T57	3		T58	2		T243	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T322	1		T292	1		T318	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T58	1		T266	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T57	1		T58	1		T243	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T57	8		T58	5		T243	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T326	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T57	1		T321	2		T322	1