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Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr18.field0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr18.field0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr18.field0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr19.field0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr19.field0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr19.field0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field5
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field6

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field6
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field7
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field8
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field9
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field9

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field9
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field2
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field2

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field2
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field3
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field3

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field3
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field4
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field4

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field4
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field5
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field5

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field5
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field6
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field6

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field6
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field7
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field7

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field7
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field8
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field8

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field8
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field1
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field1

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field1
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr8.field0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr8.field0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr8.field0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2


Group Instance : lockable_field_cov_of_flash_ctrl_prim_reg_block.csr9.field0
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr9.field0

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 2 0 2 100.00


Variables for Group Instance lockable_field_cov_of_flash_ctrl_prim_reg_block.csr9.field0
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_regwen 2 0 2 100.00 100 1 1 2

Go back
Group Instances:
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr18.field0
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr19.field0
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field0
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field1
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field2
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field3
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field4
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field5
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field6
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field7
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field8
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr3.field9
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field0
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field1
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field2
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr4.field3
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field0
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field1
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field2
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field3
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr5.field4
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field0
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field1
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field2
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field3
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field4
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field5
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field6
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field7
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr6.field8
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field0
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr7.field1
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr8.field0
lockable_field_cov_of_flash_ctrl_prim_reg_block.csr9.field0

Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 492 1 T57 2 T148 128 T58 4
auto[1] 410 1 T57 6 T58 9 T243 5


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 497 1 T57 1 T148 64 T58 4
auto[1] 575 1 T59 1 T57 11 T148 64


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 603 1 T59 1 T57 5 T148 128
auto[1] 687 1 T57 14 T58 16 T250 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 572 1 T59 1 T57 4 T148 120
auto[1] 610 1 T57 15 T58 16 T250 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 534 1 T59 1 T57 5 T148 112
auto[1] 676 1 T57 13 T58 13 T250 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 501 1 T59 1 T57 4 T148 106
auto[1] 565 1 T57 13 T58 16 T250 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 466 1 T59 1 T57 3 T148 100
auto[1] 520 1 T57 13 T58 16 T250 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 442 1 T59 1 T57 5 T148 94
auto[1] 602 1 T57 13 T58 17 T250 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 360 1 T59 1 T57 1 T148 88
auto[1] 258 1 T57 8 T58 7 T64 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 398 1 T59 1 T57 5 T148 86
auto[1] 678 1 T57 13 T58 15 T250 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 357 1 T59 1 T57 2 T148 80
auto[1] 547 1 T57 8 T58 12 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 338 1 T57 3 T148 76 T58 3
auto[1] 406 1 T57 13 T58 13 T250 2


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 568 1 T59 1 T57 4 T148 128
auto[1] 806 1 T57 10 T58 15 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 531 1 T57 4 T148 122 T58 5
auto[1] 731 1 T57 15 T58 12 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 503 1 T59 1 T57 4 T148 116
auto[1] 688 1 T57 13 T58 13 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 468 1 T59 1 T57 4 T148 110
auto[1] 808 1 T57 15 T58 13 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 594 1 T57 4 T148 128 T58 5
auto[1] 536 1 T59 1 T57 15 T58 11


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 546 1 T57 2 T148 122 T58 4
auto[1] 388 1 T57 14 T58 14 T64 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 552 1 T57 4 T148 118 T58 5
auto[1] 560 1 T59 1 T57 16 T58 15


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 459 1 T57 4 T148 100 T58 4
auto[1] 550 1 T59 1 T57 16 T58 13


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 403 1 T57 3 T148 90 T58 5
auto[1] 542 1 T59 1 T57 15 T58 14


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 526 1 T59 1 T57 6 T148 128
auto[1] 565 1 T57 13 T58 16 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 500 1 T59 1 T57 5 T148 122
auto[1] 648 1 T57 14 T58 17 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 478 1 T59 1 T57 6 T148 116
auto[1] 668 1 T57 14 T58 17 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 385 1 T59 1 T57 6 T148 100
auto[1] 536 1 T57 13 T58 14 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 338 1 T57 5 T148 94 T58 3
auto[1] 532 1 T57 11 T58 13 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 324 1 T57 3 T148 90 T58 3
auto[1] 541 1 T57 11 T58 12 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 310 1 T59 1 T57 5 T148 86
auto[1] 342 1 T57 10 T58 17 T243 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 264 1 T59 1 T57 5 T148 82
auto[1] 288 1 T57 7 T58 10 T243 4


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 257 1 T59 1 T57 4 T148 80
auto[1] 456 1 T57 8 T58 7 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 640 1 T57 5 T148 128 T58 7
auto[1] 552 1 T59 1 T57 15 T58 13


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 560 1 T57 5 T148 112 T58 7
auto[1] 550 1 T59 1 T57 15 T58 13


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 543 1 T59 1 T57 5 T148 128
auto[1] 767 1 T57 15 T58 15 T251 1


Summary for Variable cp_regwen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_regwen

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 571 1 T59 1 T57 4 T148 128
auto[1] 536 1 T57 16 T58 15 T251 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%