Unified Coverage Report :: Module :: flash_phy_rd_buf_dep

Module : flash_phy_rd_buf_dep

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.48	100.00	89.91			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.36	100.00	89.45			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Module : flash_phy_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23
1	1	Covered	T1,T2,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T23
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

---

Branch Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T5
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	783402090	7064932	0	0
BufferDepRsp_A	783402090	781836590	0	0
BufferIncrOverFlow_A	783402090	7064947	0	0
DepBufferRspOrder_A	783402091	16940316	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783402090	7064932	0	0
T1	7216	30	0	0
T2	230078	512	0	0
T3	6760	0	0	0
T4	1082652	0	0	0
T5	331238	3136	0	0
T6	0	888	0	0
T7	0	21227	0	0
T8	0	23940	0	0
T12	2100	1	0	0
T13	217126	10240	0	0
T20	5966	0	0	0
T21	3044	0	0	0
T22	5038	0	0	0
T23	0	142	0	0
T25	0	1665	0	0
T27	0	10061	0	0
T31	0	5904	0	0
T44	0	13223	0	0
T46	0	110	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783402090	781836590	0	0
T1	7216	7100	0	0
T2	230078	229880	0	0
T3	6760	5498	0	0
T4	1082652	1082634	0	0
T5	331238	311294	0	0
T12	2100	1916	0	0
T13	217126	217120	0	0
T20	5966	5852	0	0
T21	3044	2914	0	0
T22	5038	4892	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783402090	7064947	0	0
T1	7216	30	0	0
T2	230078	512	0	0
T3	6760	0	0	0
T4	1082652	0	0	0
T5	331238	3136	0	0
T6	0	888	0	0
T7	0	21227	0	0
T8	0	23940	0	0
T12	2100	1	0	0
T13	217126	10240	0	0
T20	5966	0	0	0
T21	3044	0	0	0
T22	5038	0	0	0
T23	0	142	0	0
T25	0	1665	0	0
T27	0	10061	0	0
T31	0	5904	0	0
T44	0	13223	0	0
T46	0	110	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	783402091	16940316	0	0
T1	7216	62	0	0
T2	230078	544	0	0
T3	6760	164	0	0
T4	1082652	32	0	0
T5	331238	7360	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	2100	33	0	0
T13	217126	537696	0	0
T20	5966	32	0	0
T21	3044	32	0	0
T22	5038	32	0	0
T23	0	59	0	0
T25	0	1665	0	0
T27	0	10061	0	0
T44	0	13223	0	0
T46	0	110	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T23,T45
1	1	Covered	T1,T2,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T5
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T5

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T5
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T5
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	391701045	3158531	0	0
BufferDepRsp_A	391701045	390918295	0	0
BufferIncrOverFlow_A	391701045	3158537	0	0
DepBufferRspOrder_A	391701045	8525354	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	3158531	0	0
T1	3608	16	0	0
T2	115039	512	0	0
T3	3380	0	0	0
T4	541326	0	0	0
T5	165619	3136	0	0
T6	0	426	0	0
T7	0	11213	0	0
T8	0	11847	0	0
T12	1050	1	0	0
T13	108563	8192	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	83	0	0
T31	0	5904	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	3158537	0	0
T1	3608	16	0	0
T2	115039	512	0	0
T3	3380	0	0	0
T4	541326	0	0	0
T5	165619	3136	0	0
T6	0	426	0	0
T7	0	11213	0	0
T8	0	11847	0	0
T12	1050	1	0	0
T13	108563	8192	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	83	0	0
T31	0	5904	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	8525354	0	0
T1	3608	48	0	0
T2	115039	544	0	0
T3	3380	164	0	0
T4	541326	32	0	0
T5	165619	7360	0	0
T12	1050	33	0	0
T13	108563	273504	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T32,T114
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T6

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T13,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T13,T6

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T13,T6
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T44
1	1	Covered	T1,T13,T6

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T13,T6
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T44
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T13,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T6

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T13,T6

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T13,T6
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T13,T6
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	391701045	3906401	0	0
BufferDepRsp_A	391701045	390918295	0	0
BufferIncrOverFlow_A	391701045	3906410	0	0
DepBufferRspOrder_A	391701046	8414962	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	3906401	0	0
T1	3608	14	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	0	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	2048	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	59	0	0
T25	0	1665	0	0
T27	0	10061	0	0
T44	0	13223	0	0
T46	0	110	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	3906410	0	0
T1	3608	14	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	0	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	2048	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	59	0	0
T25	0	1665	0	0
T27	0	10061	0	0
T44	0	13223	0	0
T46	0	110	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701046	8414962	0	0
T1	3608	14	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	0	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	264192	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	59	0	0
T25	0	1665	0	0
T27	0	10061	0	0
T44	0	13223	0	0
T46	0	110	0	0