Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1566804180	1563673180	0	0
CheckNGreaterZero_A	4232	4232	0	0
GntImpliesReady_A	1566804180	452667751	0	0
GntImpliesValid_A	1566804180	452667751	0	0
GrantKnown_A	1566804180	1563673180	0	0
IdxKnown_A	1566804180	1563673180	0	0
IndexIsCorrect_A	1566804180	452667751	0	0
NoReadyValidNoGrant_A	1566804180	180273295	0	0
Priority_A	1566804180	477206438	0	0
ReadyAndValidImplyGrant_A	1566804180	452667751	0	0
ReqAndReadyImplyGrant_A	1566804180	452667751	0	0
ReqImpliesValid_A	1566804180	477206438	0	0
ValidKnown_A	1566804180	1563673180	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	1563673180	0	0
T1	14432	14200	0	0
T2	460156	459760	0	0
T3	13520	10996	0	0
T4	2165304	2165268	0	0
T5	662476	622588	0	0
T12	4200	3832	0	0
T13	434252	434240	0	0
T20	11932	11704	0	0
T21	6088	5828	0	0
T22	10076	9784	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4232	4232	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T12	4	4	0	0
T13	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0
T22	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	452667751	0	0
T1	14432	2788	0	0
T2	460156	2128	0	0
T3	13520	354	0	0
T4	2165304	1077936	0	0
T5	662476	205040	0	0
T6	0	924	0	0
T7	0	20028	0	0
T8	0	24186	0	0
T12	4200	66	0	0
T13	434252	1088164	0	0
T20	11932	64	0	0
T21	6088	64	0	0
T22	10076	64	0	0
T23	0	2872	0	0
T25	0	1275562	0	0
T27	0	20122	0	0
T44	0	26446	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	452667751	0	0
T1	14432	2788	0	0
T2	460156	2128	0	0
T3	13520	354	0	0
T4	2165304	1077936	0	0
T5	662476	205040	0	0
T6	0	924	0	0
T7	0	20028	0	0
T8	0	24186	0	0
T12	4200	66	0	0
T13	434252	1088164	0	0
T20	11932	64	0	0
T21	6088	64	0	0
T22	10076	64	0	0
T23	0	2872	0	0
T25	0	1275562	0	0
T27	0	20122	0	0
T44	0	26446	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	1563673180	0	0
T1	14432	14200	0	0
T2	460156	459760	0	0
T3	13520	10996	0	0
T4	2165304	2165268	0	0
T5	662476	622588	0	0
T12	4200	3832	0	0
T13	434252	434240	0	0
T20	11932	11704	0	0
T21	6088	5828	0	0
T22	10076	9784	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	1563673180	0	0
T1	14432	14200	0	0
T2	460156	459760	0	0
T3	13520	10996	0	0
T4	2165304	2165268	0	0
T5	662476	622588	0	0
T12	4200	3832	0	0
T13	434252	434240	0	0
T20	11932	11704	0	0
T21	6088	5828	0	0
T22	10076	9784	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	452667751	0	0
T1	14432	2788	0	0
T2	460156	2128	0	0
T3	13520	354	0	0
T4	2165304	1077936	0	0
T5	662476	205040	0	0
T6	0	924	0	0
T7	0	20028	0	0
T8	0	24186	0	0
T12	4200	66	0	0
T13	434252	1088164	0	0
T20	11932	64	0	0
T21	6088	64	0	0
T22	10076	64	0	0
T23	0	2872	0	0
T25	0	1275562	0	0
T27	0	20122	0	0
T44	0	26446	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	180273295	0	0
T1	14432	352	0	0
T2	460156	2816	0	0
T3	13520	1308	0	0
T4	2165304	3392	0	0
T5	662476	49040	0	0
T6	0	1372	0	0
T7	0	24900	0	0
T8	0	64358	0	0
T12	4200	264	0	0
T13	434252	425034	0	0
T20	11932	256	0	0
T21	6088	256	0	0
T22	10076	256	0	0
T23	0	184	0	0
T25	0	5008	0	0
T27	0	57106	0	0
T44	0	900600	0	0
T46	0	338	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	477206438	0	0
T1	14432	2788	0	0
T2	460156	2128	0	0
T3	13520	354	0	0
T4	2165304	1077936	0	0
T5	662476	205040	0	0
T6	0	924	0	0
T7	0	25724	0	0
T8	0	25522	0	0
T12	4200	66	0	0
T13	434252	1088164	0	0
T20	11932	64	0	0
T21	6088	64	0	0
T22	10076	64	0	0
T23	0	2872	0	0
T25	0	1275562	0	0
T27	0	21466	0	0
T44	0	234646	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	452667751	0	0
T1	14432	2788	0	0
T2	460156	2128	0	0
T3	13520	354	0	0
T4	2165304	1077936	0	0
T5	662476	205040	0	0
T6	0	924	0	0
T7	0	20028	0	0
T8	0	24186	0	0
T12	4200	66	0	0
T13	434252	1088164	0	0
T20	11932	64	0	0
T21	6088	64	0	0
T22	10076	64	0	0
T23	0	2872	0	0
T25	0	1275562	0	0
T27	0	20122	0	0
T44	0	26446	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	452667751	0	0
T1	14432	2788	0	0
T2	460156	2128	0	0
T3	13520	354	0	0
T4	2165304	1077936	0	0
T5	662476	205040	0	0
T6	0	924	0	0
T7	0	20028	0	0
T8	0	24186	0	0
T12	4200	66	0	0
T13	434252	1088164	0	0
T20	11932	64	0	0
T21	6088	64	0	0
T22	10076	64	0	0
T23	0	2872	0	0
T25	0	1275562	0	0
T27	0	20122	0	0
T44	0	26446	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	477206438	0	0
T1	14432	2788	0	0
T2	460156	2128	0	0
T3	13520	354	0	0
T4	2165304	1077936	0	0
T5	662476	205040	0	0
T6	0	924	0	0
T7	0	25724	0	0
T8	0	25522	0	0
T12	4200	66	0	0
T13	434252	1088164	0	0
T20	11932	64	0	0
T21	6088	64	0	0
T22	10076	64	0	0
T23	0	2872	0	0
T25	0	1275562	0	0
T27	0	21466	0	0
T44	0	234646	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1566804180	1563673180	0	0
T1	14432	14200	0	0
T2	460156	459760	0	0
T3	13520	10996	0	0
T4	2165304	2165268	0	0
T5	662476	622588	0	0
T12	4200	3832	0	0
T13	434252	434240	0	0
T20	11932	11704	0	0
T21	6088	5828	0	0
T22	10076	9784	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391701045	390918295	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	391701045	115691267	0	0
GntImpliesValid_A	391701045	115691267	0	0
GrantKnown_A	391701045	390918295	0	0
IdxKnown_A	391701045	390918295	0	0
IndexIsCorrect_A	391701045	115691267	0	0
NoReadyValidNoGrant_A	391701045	46136888	0	0
Priority_A	391701045	122065670	0	0
ReadyAndValidImplyGrant_A	391701045	115691267	0	0
ReqAndReadyImplyGrant_A	391701045	115691267	0	0
ReqImpliesValid_A	391701045	122065670	0	0
ValidKnown_A	391701045	390918295	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115691267	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115691267	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115691267	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	46136888	0	0
T1	3608	153	0	0
T2	115039	1408	0	0
T3	3380	654	0	0
T4	541326	1696	0	0
T5	165619	24520	0	0
T12	1050	132	0	0
T13	108563	107353	0	0
T20	2983	128	0	0
T21	1522	128	0	0
T22	2519	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	122065670	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115691267	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115691267	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	122065670	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T23
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T7,T23

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T23
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T27
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T23

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391701045	390918295	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	391701045	115675710	0	0
GntImpliesValid_A	391701045	115675710	0	0
GrantKnown_A	391701045	390918295	0	0
IdxKnown_A	391701045	390918295	0	0
IndexIsCorrect_A	391701045	115675710	0	0
NoReadyValidNoGrant_A	391701045	46136891	0	0
Priority_A	391701045	122050110	0	0
ReadyAndValidImplyGrant_A	391701045	115675710	0	0
ReqAndReadyImplyGrant_A	391701045	115675710	0	0
ReqImpliesValid_A	391701045	122050110	0	0
ValidKnown_A	391701045	390918295	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115675710	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115675710	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115675710	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	46136891	0	0
T1	3608	153	0	0
T2	115039	1408	0	0
T3	3380	654	0	0
T4	541326	1696	0	0
T5	165619	24520	0	0
T12	1050	132	0	0
T13	108563	107353	0	0
T20	2983	128	0	0
T21	1522	128	0	0
T22	2519	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	122050110	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115675710	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	115675710	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	122050110	0	0
T1	3608	637	0	0
T2	115039	1064	0	0
T3	3380	177	0	0
T4	541326	264618	0	0
T5	165619	102520	0	0
T12	1050	33	0	0
T13	108563	274557	0	0
T20	2983	32	0	0
T21	1522	32	0	0
T22	2519	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T13
1	0	Covered	T6,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T1,T4,T13
1	1	Covered	T6,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T4,T13

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T27
1	1	Covered	T1,T4,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391701045	390918295	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	391701045	110650387	0	0
GntImpliesValid_A	391701045	110650387	0	0
GrantKnown_A	391701045	390918295	0	0
IdxKnown_A	391701045	390918295	0	0
IndexIsCorrect_A	391701045	110650387	0	0
NoReadyValidNoGrant_A	391701045	43999758	0	0
Priority_A	391701045	116545329	0	0
ReadyAndValidImplyGrant_A	391701045	110650387	0	0
ReqAndReadyImplyGrant_A	391701045	110650387	0	0
ReqImpliesValid_A	391701045	116545329	0	0
ValidKnown_A	391701045	390918295	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	43999758	0	0
T1	3608	23	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	0	0	0
T5	165619	0	0	0
T6	0	686	0	0
T7	0	12450	0	0
T8	0	32179	0	0
T12	1050	0	0	0
T13	108563	105164	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	92	0	0
T25	0	2504	0	0
T27	0	28553	0	0
T44	0	450300	0	0
T46	0	169	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	116545329	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	12862	0	0
T8	0	12761	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10733	0	0
T44	0	117323	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	116545329	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	12862	0	0
T8	0	12761	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10733	0	0
T44	0	117323	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T13
1	0	Covered	T6,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T6,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T27
1	0	Covered	T1,T4,T13
1	1	Covered	T6,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T4,T13

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T27
1	1	Covered	T1,T4,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391701045	390918295	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	391701045	110650387	0	0
GntImpliesValid_A	391701045	110650387	0	0
GrantKnown_A	391701045	390918295	0	0
IdxKnown_A	391701045	390918295	0	0
IndexIsCorrect_A	391701045	110650387	0	0
NoReadyValidNoGrant_A	391701045	43999758	0	0
Priority_A	391701045	116545329	0	0
ReadyAndValidImplyGrant_A	391701045	110650387	0	0
ReqAndReadyImplyGrant_A	391701045	110650387	0	0
ReqImpliesValid_A	391701045	116545329	0	0
ValidKnown_A	391701045	390918295	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	43999758	0	0
T1	3608	23	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	0	0	0
T5	165619	0	0	0
T6	0	686	0	0
T7	0	12450	0	0
T8	0	32179	0	0
T12	1050	0	0	0
T13	108563	105164	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	92	0	0
T25	0	2504	0	0
T27	0	28553	0	0
T44	0	450300	0	0
T46	0	169	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	116545329	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	12862	0	0
T8	0	12761	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10733	0	0
T44	0	117323	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	110650387	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	10014	0	0
T8	0	12093	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10061	0	0
T44	0	13223	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	116545329	0	0
T1	3608	757	0	0
T2	115039	0	0	0
T3	3380	0	0	0
T4	541326	274350	0	0
T5	165619	0	0	0
T6	0	462	0	0
T7	0	12862	0	0
T8	0	12761	0	0
T12	1050	0	0	0
T13	108563	269525	0	0
T20	2983	0	0	0
T21	1522	0	0	0
T22	2519	0	0	0
T23	0	1436	0	0
T25	0	637781	0	0
T27	0	10733	0	0
T44	0	117323	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391701045	390918295	0	0
T1	3608	3550	0	0
T2	115039	114940	0	0
T3	3380	2749	0	0
T4	541326	541317	0	0
T5	165619	155647	0	0
T12	1050	958	0	0
T13	108563	108560	0	0
T20	2983	2926	0	0
T21	1522	1457	0	0
T22	2519	2446	0	0