Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	394268980	37221164	0	0
DepthKnown_A	394268980	393398107	0	0
RvalidKnown_A	394268980	393398107	0	0
WreadyKnown_A	394268980	393398107	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	37221164	0	0
T17	1118	15	0	0
T54	1152	124	0	0
T55	699	57	0	0
T56	2351	1303	0	0
T57	56265	17110	0	0
T59	1546	745	0	0
T60	883	21	0	0
T61	1356	124	0	0
T62	1291	57	0	0
T63	4250	514	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T17	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	394268980	39329564	0	0
DepthKnown_A	394268980	393398107	0	0
RvalidKnown_A	394268980	393398107	0	0
WreadyKnown_A	394268980	393398107	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	39329564	0	0
T17	1118	15	0	0
T54	1152	124	0	0
T55	699	57	0	0
T56	2351	705	0	0
T57	56265	10314	0	0
T59	1546	402	0	0
T60	883	21	0	0
T61	1356	124	0	0
T62	1291	57	0	0
T63	4250	472	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T17	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	394268980	7017875	0	0
DepthKnown_A	394268980	393398107	0	0
RvalidKnown_A	394268980	393398107	0	0
WreadyKnown_A	394268980	393398107	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	7017875	0	0
T56	2351	386	0	0
T57	56265	0	0	0
T58	31383	0	0	0
T59	1546	0	0	0
T61	1356	0	0	0
T62	1291	0	0	0
T63	4250	0	0	0
T64	0	77	0	0
T139	3038	18	0	0
T140	0	545	0	0
T141	0	86	0	0
T142	0	83	0	0
T143	0	118	0	0
T144	0	150	0	0
T145	0	183	0	0
T146	0	94	0	0
T147	1365	0	0	0
T148	308986	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T17	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	394268980	3038888	0	0
DepthKnown_A	394268980	393398107	0	0
RvalidKnown_A	394268980	393398107	0	0
WreadyKnown_A	394268980	393398107	0	0
gen_passthru_fifo.paramCheckPass	1273	1273	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	3038888	0	0
T56	2351	235	0	0
T57	56265	0	0	0
T58	31383	0	0	0
T59	1546	0	0	0
T61	1356	0	0	0
T62	1291	0	0	0
T63	4250	0	0	0
T64	0	192	0	0
T139	3038	18	0	0
T140	0	425	0	0
T141	0	74	0	0
T142	0	82	0	0
T143	0	99	0	0
T144	0	108	0	0
T145	0	92	0	0
T146	0	81	0	0
T147	1365	0	0	0
T148	308986	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	394268980	393398107	0	0
T17	1118	1068	0	0
T54	1152	1069	0	0
T55	699	636	0	0
T56	2351	2290	0	0
T57	56265	52021	0	0
T59	1546	1479	0	0
T60	883	832	0	0
T61	1356	1292	0	0
T62	1291	1222	0	0
T63	4250	4039	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1273	1273	0	0
T17	1	1	0	0
T54	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0