Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_phy_rd
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.48 100.00 89.91 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd 97.36 100.00 89.45 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd 97.48 100.00 89.91 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.36 100.00 89.45 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.53 99.15 93.05 100.00 99.25 96.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.36 100.00 83.96 100.00 97.83 100.00 gen_flash_cores[1].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[1].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[2].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[3].u_rd_buf 94.64 100.00 78.57 100.00 100.00
u_bus_intg 100.00 100.00
u_dec 100.00 100.00 100.00
u_intg_buf 100.00 100.00
u_mask_storage 92.90 100.00 78.26 93.33 100.00
u_plain_enc 100.00 100.00
u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
u_rd_storage 96.55 100.00 82.76 100.00 100.00 100.00
u_rsp_order_fifo 96.55 100.00 82.76 100.00 100.00 100.00
u_valid_random 94.17 92.31 97.69 100.00 86.67


Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.48 100.00 89.91 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.57 99.15 93.22 100.00 99.25 96.23


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.87 100.00 91.51 100.00 97.83 100.00 gen_flash_cores[0].u_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_bufs[0].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[1].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[2].u_rd_buf 94.64 100.00 78.57 100.00 100.00
gen_bufs[3].u_rd_buf 94.64 100.00 78.57 100.00 100.00
u_bus_intg 100.00 100.00
u_dec 100.00 100.00 100.00
u_intg_buf 100.00 100.00
u_mask_storage 92.90 100.00 78.26 93.33 100.00
u_plain_enc 100.00 100.00
u_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
u_rd_storage 96.55 100.00 82.76 100.00 100.00 100.00
u_rsp_order_fifo 96.55 100.00 82.76 100.00 100.00 100.00
u_valid_random 94.17 92.31 97.69 100.00 86.67

Line Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
TOTAL118118100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23111100.00
ALWAYS25644100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN32011100.00
CONT_ASSIGN32511100.00
ALWAYS3541212100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN43011100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN43911100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN50011100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50811100.00
ALWAYS56255100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN57911100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN59011100.00
CONT_ASSIGN59811100.00
CONT_ASSIGN61511100.00
CONT_ASSIGN62011100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62511100.00
ALWAYS63166100.00
CONT_ASSIGN64211100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65511100.00
CONT_ASSIGN67611100.00
CONT_ASSIGN68811100.00
CONT_ASSIGN69111100.00
CONT_ASSIGN69511100.00
CONT_ASSIGN69811100.00
CONT_ASSIGN70111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
136 1 1
139 4 4
140 4 4
145 4 4
151 1 1
153 3 3
185 1 1
192 4 4
193 4 4
195 4 4
211 4 4
217 4 4
221 4 4
228 1 1
231 1 1
256 1 1
257 1 1
258 1 1
259 1 1
MISSING_ELSE
289 1 1
296 1 1
299 1 1
302 1 1
320 1 1
325 1 1
354 1 1
355 1 1
356 1 1
357 1 1
358 1 1
359 1 1
360 1 1
361 1 1
362 1 1
363 1 1
365 1 1
366 1 1
MISSING_ELSE
371 1 1
376 1 1
387 1 1
393 1 1
398 1 1
416 1 1
420 1 1
430 1 1
433 1 1
439 1 1
444 1 1
447 1 1
469 1 1
475 1 1
479 1 1
483 1 1
500 1 1
504 1 1
507 1 1
508 1 1
562 1 1
563 1 1
564 1 1
565 1 1
566 1 1
567 unreachable
MISSING_ELSE
572 1 1
576 1 1
579 1 1
586 1 1
590 1 1
598 1 1
615 1 1
620 1 1
625 4 4
631 1 1
632 1 1
633 1 1
634 1 1
635 1 1
636 1 1
MISSING_ELSE
642 1 1
654 1 1
655 1 1
676 1 1
688 1 1
691 1 1
695 1 1
698 1 1
701 1 1

Cond Coverage for Module : flash_phy_rd
TotalCoveredPercent
Conditions43639289.91
Logical43639289.91
Non-Logical00
Event00

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT39,T40,T78
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT39,T40,T78 

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT39,T40,T78
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT39,T40,T78 

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT39,T40,T78
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT39,T40,T78 

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT39,T40,T124
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT39,T40,T124 

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T5
01Not Covered
10CoveredT1,T2,T3 

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3 

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T5
1011111Not Covered
1101111CoveredT5,T23,T31
1110111CoveredT1,T2,T5
1111011CoveredT39,T40,T78
1111101Not Covered
1111110CoveredT7,T39,T75
1111111CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T5
1011111Not Covered
1101111CoveredT5,T23,T31
1110111CoveredT1,T2,T5
1111011CoveredT39,T40,T78
1111101Not Covered
1111110CoveredT7,T27,T39
1111111CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T5
1011111Not Covered
1101111CoveredT5,T23,T31
1110111CoveredT1,T2,T5
1111011CoveredT39,T40,T78
1111101CoveredT203,T204
1111110CoveredT75,T205,T206
1111111CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T5
1011111Not Covered
1101111CoveredT5,T23,T31
1110111CoveredT1,T2,T5
1111011CoveredT39,T40,T81
1111101Not Covered
1111110CoveredT7,T81,T82
1111111CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T39,T75
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T39
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT75,T205,T206
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T81,T82
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T44
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T44
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T44
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T44
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT5,T13,T31
10CoveredT1,T2,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T13,T31
010CoveredT5,T13,T31
100CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT5,T13,T31 

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT5,T13,T31
10CoveredT1,T2,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T13,T31
010CoveredT5,T13,T31
100CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT5,T13,T31 

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT5,T13,T31
10CoveredT1,T2,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T13,T31
010CoveredT5,T13,T31
100CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT5,T13,T31 

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT5,T13,T31
10CoveredT1,T2,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T13,T31
010CoveredT5,T13,T31
100CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT5,T13,T31 

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT39,T75,T76
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T8,T39
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T27,T44
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T39,T75
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       289
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       296
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       299
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T8,T27
11CoveredT1,T2,T3 

 LINE       302
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       358
 EXPRESSION (req_o && ack_i)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT75,T76,T28
11CoveredT1,T2,T3 

 LINE       371
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       376
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT18,T19,T137
11CoveredT1,T2,T3 

 LINE       387
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       393
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change)
             --------------------------------1-------------------------------   -----------2-----------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3 

 LINE       393
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       393
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT6,T7,T8
111CoveredT1,T2,T3 

 LINE       398
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match)
             --1--   --------2-------   ----3----   ------4------   ----5---
-1--2--3--4--5-StatusTests
01111CoveredT1,T2,T3
10111CoveredT182
11011CoveredT7,T8,T27
11101Not Covered
11110CoveredT1,T2,T5
11111CoveredT1,T2,T3 

 LINE       416
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T13,T6
11CoveredT1,T2,T3 

 LINE       420
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT7,T25,T46 

 LINE       420
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       430
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT4,T13,T44
10CoveredT1,T2,T3
11CoveredT39,T40,T124 

 LINE       439
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T39 

 LINE       439
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T27,T39
10CoveredT39,T40,T124 

 LINE       444
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT4,T13,T8
10CoveredT1,T2,T3
11CoveredT8,T27,T39 

 LINE       469
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT18,T19,T137
10Not Covered
11CoveredT1,T2,T3 

 LINE       475
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       475
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       479
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T13,T6
110CoveredT84,T207,T169
111CoveredT1,T2,T3 

 LINE       483
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT39,T69,T208
111CoveredT1,T13,T6 

 LINE       500
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T13,T6 

 LINE       504
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3 

 LINE       507
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T13,T6
11CoveredT1,T2,T3 

 LINE       508
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T13,T6 

 LINE       539
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01UnreachableT5,T13,T31
10CoveredT1,T2,T3
11UnreachableT1,T2,T3 

 LINE       564
 EXPRESSION (req_o && ack_i && descramble_i)
             --1--    --2--    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT76,T41,T78
110CoveredT1,T13,T6
111CoveredT1,T2,T3 

 LINE       566
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----
-1--2-StatusTests
01UnreachableT5,T13,T31
10CoveredT1,T2,T3
11UnreachableT1,T2,T3 

 LINE       576
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT84,T207,T169
111CoveredT1,T2,T3 

 LINE       586
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       586
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       590
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       590
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------
-1-StatusTests
0CoveredT1,T13,T6
1CoveredT1,T2,T3 

 LINE       598
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T13,T6 

 LINE       598
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT1,T13,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       615
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       615
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       615
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT1,T13,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       620
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT18,T19,T137
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3 

 LINE       620
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T3
10Not Covered 

 LINE       620
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T5
1110CoveredT1,T2,T5
1111CoveredT1,T2,T5 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T5
1110CoveredT1,T2,T5
1111CoveredT1,T2,T5 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T5
1110CoveredT1,T2,T5
1111CoveredT1,T2,T5 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T5
1110CoveredT1,T2,T5
1111CoveredT1,T2,T5 

 LINE       636
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T5
01Not Covered
10Not Covered 

 LINE       642
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       655
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49,T39,T164 

 LINE       676
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       676
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       688
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T3 

 LINE       691
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT49,T39,T164 

 LINE       691
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT49,T39,T164 

 LINE       691
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T2,T3
100CoveredT39,T40,T78 

 LINE       691
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T5
11Not Covered 

 LINE       695
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT49,T39,T164
Branch Coverage for Module : flash_phy_rd
Line No.TotalCoveredPercent
Branches 39 39 100.00
TERNARY 185 2 2 100.00
TERNARY 231 2 2 100.00
TERNARY 296 2 2 100.00
TERNARY 439 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 586 3 3 100.00
TERNARY 590 3 3 100.00
TERNARY 615 3 3 100.00
TERNARY 642 2 2 100.00
TERNARY 676 2 2 100.00
TERNARY 655 2 2 100.00
TERNARY 166 2 2 100.00
IF 256 3 3 100.00
IF 354 4 4 100.00
IF 562 3 3 100.00
IF 634 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5 



	LineNo.	Expression
-1-:	231	(no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5 



	LineNo.	Expression
-1-:	296	((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	439	((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T8,T27,T39
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	475	(hint_descram) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	586	(forward) ? 
-2-:	586	(hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T13,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	590	(forward) ? 
-2-:	590	((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T13,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T13,T6 



	LineNo.	Expression
-1-:	615	(forward) ? 
-2-:	615	(((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T13,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	642	((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	676	(rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	655	(data_err_o) ?

Branches:
-1-StatusTests
1 Covered T49,T39,T164
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5 



	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	354	if ((!rst_ni))
-2-:	358	if ((req_o && ack_i))
-3-:	365	if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	562	if ((!rst_ni))
-2-:	564	if (((req_o && ack_i) && descramble_i))
-3-:	566	if ((calc_req_o && calc_ack_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Unreachable T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	634	if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3

Assert Coverage for Module : flash_phy_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 783402090 1467494 0 0
ExclusiveOps_A 783402090 781836590 0 0
ExclusiveProgHazard_A 783402090 781836590 0 0
ExclusiveState_A 783402090 781836590 0 0
ForwardCheck_A 783402090 4303039 0 0
IdleCheck_A 783402090 104118011 0 0
MaxBufs_A 2116 2116 0 0
OneHotAlloc_A 783402090 781836590 0 0
OneHotMatch_A 783402090 781836590 0 0
OneHotRspMatch_A 783402090 781836590 0 0
OneHotUpdate_A 783402090 781836590 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 1467494 0 0
T1 7216 12 0 0
T2 230078 256 0 0
T3 6760 0 0 0
T4 1082652 0 0 0
T5 331238 1640 0 0
T6 0 419 0 0
T7 0 1768 0 0
T8 0 3161 0 0
T12 2100 0 0 0
T13 217126 5120 0 0
T20 5966 0 0 0
T21 3044 0 0 0
T22 5038 0 0 0
T23 0 65 0 0
T25 0 826 0 0
T27 0 1991 0 0
T31 0 3084 0 0
T44 0 2336 0 0
T46 0 51 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 781836590 0 0
T1 7216 7100 0 0
T2 230078 229880 0 0
T3 6760 5498 0 0
T4 1082652 1082634 0 0
T5 331238 311294 0 0
T12 2100 1916 0 0
T13 217126 217120 0 0
T20 5966 5852 0 0
T21 3044 2914 0 0
T22 5038 4892 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 781836590 0 0
T1 7216 7100 0 0
T2 230078 229880 0 0
T3 6760 5498 0 0
T4 1082652 1082634 0 0
T5 331238 311294 0 0
T12 2100 1916 0 0
T13 217126 217120 0 0
T20 5966 5852 0 0
T21 3044 2914 0 0
T22 5038 4892 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 781836590 0 0
T1 7216 7100 0 0
T2 230078 229880 0 0
T3 6760 5498 0 0
T4 1082652 1082634 0 0
T5 331238 311294 0 0
T12 2100 1916 0 0
T13 217126 217120 0 0
T20 5966 5852 0 0
T21 3044 2914 0 0
T22 5038 4892 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 4303039 0 0
T1 7216 18 0 0
T2 230078 0 0 0
T3 6760 0 0 0
T4 1082652 0 0 0
T5 331238 0 0 0
T6 0 469 0 0
T7 0 19459 0 0
T12 2100 0 0 0
T13 217126 5120 0 0
T20 5966 0 0 0
T21 3044 0 0 0
T22 5038 0 0 0
T23 0 77 0 0
T25 0 1924 0 0
T27 0 355 0 0
T32 0 1792 0 0
T44 0 23269 0 0
T45 0 2 0 0
T46 0 602 0 0
T121 0 3 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 104118011 0 0
T1 7216 176 0 0
T2 230078 1408 0 0
T3 6760 654 0 0
T4 1082652 1696 0 0
T5 331238 24520 0 0
T6 0 706 0 0
T7 0 19504 0 0
T8 0 37613 0 0
T12 2100 132 0 0
T13 217126 212517 0 0
T20 5966 128 0 0
T21 3044 128 0 0
T22 5038 128 0 0
T23 0 92 0 0
T25 0 2504 0 0
T27 0 32672 0 0
T44 0 557573 0 0
T46 0 169 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2116 2116 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T12 2 2 0 0
T13 2 2 0 0
T20 2 2 0 0
T21 2 2 0 0
T22 2 2 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 781836590 0 0
T1 7216 7100 0 0
T2 230078 229880 0 0
T3 6760 5498 0 0
T4 1082652 1082634 0 0
T5 331238 311294 0 0
T12 2100 1916 0 0
T13 217126 217120 0 0
T20 5966 5852 0 0
T21 3044 2914 0 0
T22 5038 4892 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 781836590 0 0
T1 7216 7100 0 0
T2 230078 229880 0 0
T3 6760 5498 0 0
T4 1082652 1082634 0 0
T5 331238 311294 0 0
T12 2100 1916 0 0
T13 217126 217120 0 0
T20 5966 5852 0 0
T21 3044 2914 0 0
T22 5038 4892 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 781836590 0 0
T1 7216 7100 0 0
T2 230078 229880 0 0
T3 6760 5498 0 0
T4 1082652 1082634 0 0
T5 331238 311294 0 0
T12 2100 1916 0 0
T13 217126 217120 0 0
T20 5966 5852 0 0
T21 3044 2914 0 0
T22 5038 4892 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 783402090 781836590 0 0
T1 7216 7100 0 0
T2 230078 229880 0 0
T3 6760 5498 0 0
T4 1082652 1082634 0 0
T5 331238 311294 0 0
T12 2100 1916 0 0
T13 217126 217120 0 0
T20 5966 5852 0 0
T21 3044 2914 0 0
T22 5038 4892 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL118118100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23111100.00
ALWAYS25644100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN32011100.00
CONT_ASSIGN32511100.00
ALWAYS3541212100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN43011100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN43911100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN50011100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50811100.00
ALWAYS56255100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN57911100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN59011100.00
CONT_ASSIGN59811100.00
CONT_ASSIGN61511100.00
CONT_ASSIGN62011100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62511100.00
ALWAYS63166100.00
CONT_ASSIGN64211100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65511100.00
CONT_ASSIGN67611100.00
CONT_ASSIGN68811100.00
CONT_ASSIGN69111100.00
CONT_ASSIGN69511100.00
CONT_ASSIGN69811100.00
CONT_ASSIGN70111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
136 1 1
139 4 4
140 4 4
145 4 4
151 1 1
153 3 3
185 1 1
192 4 4
193 4 4
195 4 4
211 4 4
217 4 4
221 4 4
228 1 1
231 1 1
256 1 1
257 1 1
258 1 1
259 1 1
MISSING_ELSE
289 1 1
296 1 1
299 1 1
302 1 1
320 1 1
325 1 1
354 1 1
355 1 1
356 1 1
357 1 1
358 1 1
359 1 1
360 1 1
361 1 1
362 1 1
363 1 1
365 1 1
366 1 1
MISSING_ELSE
371 1 1
376 1 1
387 1 1
393 1 1
398 1 1
416 1 1
420 1 1
430 1 1
433 1 1
439 1 1
444 1 1
447 1 1
469 1 1
475 1 1
479 1 1
483 1 1
500 1 1
504 1 1
507 1 1
508 1 1
562 1 1
563 1 1
564 1 1
565 1 1
566 1 1
567 unreachable
MISSING_ELSE
572 1 1
576 1 1
579 1 1
586 1 1
590 1 1
598 1 1
615 1 1
620 1 1
625 4 4
631 1 1
632 1 1
633 1 1
634 1 1
635 1 1
636 1 1
MISSING_ELSE
642 1 1
654 1 1
655 1 1
676 1 1
688 1 1
691 1 1
695 1 1
698 1 1
701 1 1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalCoveredPercent
Conditions43639089.45
Logical43639089.45
Non-Logical00
Event00

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T13,T6
01CoveredT39,T40,T78
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T13,T6
110Not Covered
111CoveredT39,T40,T78 

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T13,T6
01CoveredT39,T78,T81
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T13,T6
110Not Covered
111CoveredT39,T78,T81 

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T13,T6
01CoveredT39,T40,T78
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T13,T6
110Not Covered
111CoveredT39,T40,T78 

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T13,T6
01CoveredT39,T40,T124
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T13,T6
110Not Covered
111CoveredT39,T40,T124 

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T13,T6
10CoveredT1,T2,T3
11CoveredT1,T13,T6 

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T13,T6
10CoveredT1,T2,T3
11CoveredT1,T13,T6 

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T13,T6
10CoveredT1,T2,T3
11CoveredT1,T13,T6 

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT1,T13,T6
1CoveredT1,T2,T3 

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT1,T13,T6
01Not Covered
10CoveredT1,T2,T3 

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T13,T6 

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT1,T13,T6
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T13,T6
1011111Not Covered
1101111CoveredT73,T209,T200
1110111CoveredT1,T13,T6
1111011CoveredT40,T78,T81
1111101Not Covered
1111110CoveredT39,T75,T28
1111111CoveredT1,T13,T6 

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T13,T6
10CoveredT1,T13,T6 

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T13,T6
1011111Not Covered
1101111CoveredT116,T126,T209
1110111CoveredT1,T13,T6
1111011CoveredT81,T210,T211
1111101Not Covered
1111110CoveredT7,T27,T39
1111111CoveredT1,T13,T6 

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T13,T6
10CoveredT1,T13,T6 

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T13,T6
1011111Not Covered
1101111CoveredT122,T116,T126
1110111CoveredT1,T13,T6
1111011CoveredT40,T78,T81
1111101Not Covered
1111110CoveredT75,T206,T212
1111111CoveredT1,T13,T6 

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T13,T6
10CoveredT1,T13,T6 

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T13,T6
1011111Not Covered
1101111CoveredT122,T116,T126
1110111CoveredT1,T13,T6
1111011CoveredT39,T40,T81
1111101Not Covered
1111110CoveredT82,T213,T214
1111111CoveredT1,T13,T6 

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T13,T6
10CoveredT1,T13,T6 

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT39,T75,T28
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T39
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT75,T206,T212
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT82,T213,T214
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT44,T39,T75
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T44
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT44,T75,T205
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT44,T75,T41
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT13,T25,T46
10CoveredT1,T13,T6
11CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T32,T114
010CoveredT13,T25,T32
100CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T13
11CoveredT13,T25,T32 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T23,T25
11CoveredT13,T32,T114 

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT13,T25,T46
10CoveredT1,T13,T6
11CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T32,T114
010CoveredT13,T25,T32
100CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T13
11CoveredT13,T25,T32 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T23,T25
11CoveredT13,T32,T114 

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT13,T25,T46
10CoveredT1,T13,T6
11CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T32,T114
010CoveredT13,T25,T32
100CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T13
11CoveredT13,T25,T32 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T23,T25
11CoveredT13,T32,T114 

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT13,T25,T46
10CoveredT1,T13,T6
11CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T32,T114
010CoveredT13,T25,T32
100CoveredT13,T25,T46 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T13
11CoveredT13,T25,T32 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T23,T25
11CoveredT13,T32,T114 

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT1,T13,T6
1CoveredT1,T2,T3 

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT39,T75,T76
10CoveredT1,T2,T3
11CoveredT1,T13,T6 

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T8,T39
10CoveredT1,T2,T3
11CoveredT1,T13,T6 

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T27,T44
10CoveredT1,T2,T3
11CoveredT1,T13,T6 

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT7,T39,T75
10CoveredT1,T2,T3
11CoveredT1,T13,T6 

 LINE       289
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT1,T4,T13
10CoveredT1,T13,T6
11CoveredT1,T13,T6 

 LINE       296
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       299
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T8,T27
11CoveredT1,T13,T6 

 LINE       302
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T13,T6
11CoveredT1,T13,T6 

 LINE       358
 EXPRESSION (req_o && ack_i)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT75,T76,T28
11CoveredT1,T13,T6 

 LINE       371
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T13,T6
01CoveredT1,T13,T6
10CoveredT1,T2,T3 

 LINE       376
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT18,T19,T137
11CoveredT1,T2,T3 

 LINE       387
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       393
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change)
             --------------------------------1-------------------------------   -----------2-----------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3 

 LINE       393
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT1,T13,T6
1CoveredT1,T2,T3 

 LINE       393
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T13,T6
110CoveredT6,T7,T8
111CoveredT1,T2,T3 

 LINE       398
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match)
             --1--   --------2-------   ----3----   ------4------   ----5---
-1--2--3--4--5-StatusTests
01111CoveredT1,T2,T3
10111Not Covered
11011CoveredT7,T8,T27
11101Not Covered
11110CoveredT1,T13,T6
11111CoveredT1,T13,T6 

 LINE       416
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT13,T8,T27
10CoveredT1,T13,T6
11CoveredT13,T8,T27 

 LINE       420
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T4,T13
10CoveredT1,T13,T6
11CoveredT7,T25,T75 

 LINE       420
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T13 

 LINE       430
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT4,T13,T44
10CoveredT13,T8,T27
11CoveredT39,T40,T124 

 LINE       439
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T39 

 LINE       439
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T27,T39
10CoveredT39,T40,T124 

 LINE       444
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT4,T13,T8
10CoveredT13,T8,T27
11CoveredT8,T27,T39 

 LINE       469
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT18,T19,T137
10Not Covered
11CoveredT1,T2,T3 

 LINE       475
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T8,T27 

 LINE       475
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT13,T8,T27
11CoveredT13,T8,T27 

 LINE       479
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT13,T8,T27
101CoveredT1,T13,T6
110CoveredT84,T158,T159
111CoveredT13,T8,T27 

 LINE       483
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT13,T8,T27
110CoveredT39,T208,T215
111CoveredT1,T13,T6 

 LINE       500
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------
-1--2-StatusTests
01CoveredT13,T8,T27
10Not Covered
11CoveredT1,T13,T6 

 LINE       504
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT13,T8,T27 

 LINE       507
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T13,T6
11CoveredT13,T8,T27 

 LINE       508
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT13,T8,T27
11CoveredT1,T13,T6 

 LINE       539
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01UnreachableT13,T32,T65
10CoveredT13,T8,T27
11UnreachableT13,T8,T27 

 LINE       564
 EXPRESSION (req_o && ack_i && descramble_i)
             --1--    --2--    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT76,T41,T78
110CoveredT1,T13,T6
111CoveredT13,T8,T27 

 LINE       566
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----
-1--2-StatusTests
01UnreachableT13,T32,T65
10CoveredT13,T8,T27
11UnreachableT13,T8,T27 

 LINE       576
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT84,T158,T159
111CoveredT13,T8,T27 

 LINE       586
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       586
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T8,T27 

 LINE       590
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       590
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------
-1-StatusTests
0CoveredT1,T13,T6
1CoveredT1,T2,T3 

 LINE       598
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T8,T27
10CoveredT1,T13,T6 

 LINE       598
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT1,T13,T6
10CoveredT1,T2,T3
11CoveredT13,T8,T27 

 LINE       615
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       615
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T8,T27 

 LINE       615
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT1,T13,T6
10CoveredT1,T2,T3
11CoveredT13,T8,T27 

 LINE       620
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT18,T19,T137
101CoveredT13,T32,T114
110Not Covered
111CoveredT1,T13,T6 

 LINE       620
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------
-1--2-StatusTests
00CoveredT1,T13,T6
01CoveredT1,T2,T3
10Not Covered 

 LINE       620
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T13,T6
1110CoveredT1,T13,T6
1111CoveredT1,T13,T6 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T13,T6
1110CoveredT1,T13,T6
1111CoveredT1,T13,T6 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T13,T6
1110CoveredT1,T13,T6
1111CoveredT1,T13,T6 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T13,T6
1110CoveredT1,T13,T6
1111CoveredT1,T13,T6 

 LINE       636
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T13,T6
01Not Covered
10Not Covered 

 LINE       642
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       655
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT39,T40,T124 

 LINE       676
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T8,T27 

 LINE       676
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT13,T8,T27
1CoveredT13,T8,T27 

 LINE       688
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T13,T6
10CoveredT1,T13,T6 

 LINE       691
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT39,T40,T124 

 LINE       691
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT13,T8,T27
10CoveredT1,T13,T6
11CoveredT39,T40,T124 

 LINE       691
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT13,T8,T27
100CoveredT39,T40,T78 

 LINE       691
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T13,T6
11Not Covered 

 LINE       695
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---
-1--2-StatusTests
01CoveredT13,T8,T27
10CoveredT1,T13,T6
11CoveredT39,T40,T124
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
Line No.TotalCoveredPercent
Branches 39 39 100.00
TERNARY 185 2 2 100.00
TERNARY 231 2 2 100.00
TERNARY 296 2 2 100.00
TERNARY 439 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 586 3 3 100.00
TERNARY 590 3 3 100.00
TERNARY 615 3 3 100.00
TERNARY 642 2 2 100.00
TERNARY 676 2 2 100.00
TERNARY 655 2 2 100.00
TERNARY 166 2 2 100.00
IF 256 3 3 100.00
IF 354 4 4 100.00
IF 562 3 3 100.00
IF 634 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T13,T6 



	LineNo.	Expression
-1-:	231	(no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T13,T6 



	LineNo.	Expression
-1-:	296	((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T13,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	439	((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T8,T27,T39
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	475	(hint_descram) ?

Branches:
-1-StatusTests
1 Covered T13,T8,T27
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	586	(forward) ? 
-2-:	586	(hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T13,T6
0 1 Covered T13,T8,T27
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	590	(forward) ? 
-2-:	590	((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T13,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T13,T6 



	LineNo.	Expression
-1-:	615	(forward) ? 
-2-:	615	(((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T13,T6
0 1 Covered T13,T8,T27
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	642	((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T1,T13,T6
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	676	(rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T13,T8,T27
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	655	(data_err_o) ?

Branches:
-1-StatusTests
1 Covered T39,T40,T124
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T13,T6 



	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T13,T6 



	LineNo.	Expression
-1-:	354	if ((!rst_ni))
-2-:	358	if ((req_o && ack_i))
-3-:	365	if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T13,T6
0 0 1 Covered T1,T13,T6
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	562	if ((!rst_ni))
-2-:	564	if (((req_o && ack_i) && descramble_i))
-3-:	566	if ((calc_req_o && calc_ack_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T13,T8,T27
0 0 1 Unreachable T13,T8,T27
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	634	if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T1,T13,T6
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 391701045 921420 0 0
ExclusiveOps_A 391701045 390918295 0 0
ExclusiveProgHazard_A 391701045 390918295 0 0
ExclusiveState_A 391701045 390918295 0 0
ForwardCheck_A 391701045 2123654 0 0
IdleCheck_A 391701045 50765329 0 0
MaxBufs_A 1058 1058 0 0
OneHotAlloc_A 391701045 390918295 0 0
OneHotMatch_A 391701045 390918295 0 0
OneHotRspMatch_A 391701045 390918295 0 0
OneHotUpdate_A 391701045 390918295 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 921420 0 0
T1 3608 5 0 0
T2 115039 0 0 0
T3 3380 0 0 0
T4 541326 0 0 0
T5 165619 0 0 0
T6 0 218 0 0
T7 0 524 0 0
T8 0 1305 0 0
T12 1050 0 0 0
T13 108563 1024 0 0
T20 2983 0 0 0
T21 1522 0 0 0
T22 2519 0 0 0
T23 0 26 0 0
T25 0 826 0 0
T27 0 944 0 0
T44 0 2336 0 0
T46 0 51 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 2123654 0 0
T1 3608 9 0 0
T2 115039 0 0 0
T3 3380 0 0 0
T4 541326 0 0 0
T5 165619 0 0 0
T6 0 244 0 0
T7 0 9490 0 0
T12 1050 0 0 0
T13 108563 1024 0 0
T20 2983 0 0 0
T21 1522 0 0 0
T22 2519 0 0 0
T23 0 33 0 0
T25 0 839 0 0
T32 0 1792 0 0
T44 0 10887 0 0
T46 0 59 0 0
T121 0 3 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 50765329 0 0
T1 3608 23 0 0
T2 115039 0 0 0
T3 3380 0 0 0
T4 541326 0 0 0
T5 165619 0 0 0
T6 0 706 0 0
T7 0 19504 0 0
T8 0 37613 0 0
T12 1050 0 0 0
T13 108563 105164 0 0
T20 2983 0 0 0
T21 1522 0 0 0
T22 2519 0 0 0
T23 0 92 0 0
T25 0 2504 0 0
T27 0 32672 0 0
T44 0 557573 0 0
T46 0 169 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1058 1058 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
TOTAL118118100.00
CONT_ASSIGN13611100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN13911100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN15311100.00
CONT_ASSIGN18511100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19211100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19311100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21111100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN21711100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22111100.00
CONT_ASSIGN22811100.00
CONT_ASSIGN23111100.00
ALWAYS25644100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30211100.00
CONT_ASSIGN32011100.00
CONT_ASSIGN32511100.00
ALWAYS3541212100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39811100.00
CONT_ASSIGN41611100.00
CONT_ASSIGN42011100.00
CONT_ASSIGN43011100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN43911100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN46911100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48311100.00
CONT_ASSIGN50011100.00
CONT_ASSIGN50411100.00
CONT_ASSIGN50711100.00
CONT_ASSIGN50811100.00
ALWAYS56255100.00
CONT_ASSIGN57211100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN57911100.00
CONT_ASSIGN58611100.00
CONT_ASSIGN59011100.00
CONT_ASSIGN59811100.00
CONT_ASSIGN61511100.00
CONT_ASSIGN62011100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62511100.00
CONT_ASSIGN62511100.00
ALWAYS63166100.00
CONT_ASSIGN64211100.00
CONT_ASSIGN65411100.00
CONT_ASSIGN65511100.00
CONT_ASSIGN67611100.00
CONT_ASSIGN68811100.00
CONT_ASSIGN69111100.00
CONT_ASSIGN69511100.00
CONT_ASSIGN69811100.00
CONT_ASSIGN70111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
136 1 1
139 4 4
140 4 4
145 4 4
151 1 1
153 3 3
185 1 1
192 4 4
193 4 4
195 4 4
211 4 4
217 4 4
221 4 4
228 1 1
231 1 1
256 1 1
257 1 1
258 1 1
259 1 1
MISSING_ELSE
289 1 1
296 1 1
299 1 1
302 1 1
320 1 1
325 1 1
354 1 1
355 1 1
356 1 1
357 1 1
358 1 1
359 1 1
360 1 1
361 1 1
362 1 1
363 1 1
365 1 1
366 1 1
MISSING_ELSE
371 1 1
376 1 1
387 1 1
393 1 1
398 1 1
416 1 1
420 1 1
430 1 1
433 1 1
439 1 1
444 1 1
447 1 1
469 1 1
475 1 1
479 1 1
483 1 1
500 1 1
504 1 1
507 1 1
508 1 1
562 1 1
563 1 1
564 1 1
565 1 1
566 1 1
567 unreachable
MISSING_ELSE
572 1 1
576 1 1
579 1 1
586 1 1
590 1 1
598 1 1
615 1 1
620 1 1
625 4 4
631 1 1
632 1 1
633 1 1
634 1 1
635 1 1
636 1 1
MISSING_ELSE
642 1 1
654 1 1
655 1 1
676 1 1
688 1 1
691 1 1
695 1 1
698 1 1
701 1 1

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalCoveredPercent
Conditions43639289.91
Logical43639289.91
Non-Logical00
Event00

 LINE       139
 EXPRESSION (read_buf[0].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       139
 EXPRESSION (read_buf[1].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       139
 EXPRESSION (read_buf[2].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       139
 EXPRESSION (read_buf[3].attr == Valid)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       140
 EXPRESSION (read_buf[0].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       140
 EXPRESSION (read_buf[1].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       140
 EXPRESSION (read_buf[2].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       140
 EXPRESSION (read_buf[3].attr == Wip)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       145
 EXPRESSION ((read_buf[0].attr == Invalid) | ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT39,T40,T78
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[0].attr == Valid) & read_buf[0].err & ((~buf_dependency[0])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT39,T40,T78 

 LINE       145
 SUB-EXPRESSION (read_buf[0].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       145
 EXPRESSION ((read_buf[1].attr == Invalid) | ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT39,T40,T78
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[1].attr == Valid) & read_buf[1].err & ((~buf_dependency[1])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT39,T40,T78 

 LINE       145
 SUB-EXPRESSION (read_buf[1].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       145
 EXPRESSION ((read_buf[2].attr == Invalid) | ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT39,T40,T78
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[2].attr == Valid) & read_buf[2].err & ((~buf_dependency[2])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT39,T40,T78 

 LINE       145
 SUB-EXPRESSION (read_buf[2].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       145
 EXPRESSION ((read_buf[3].attr == Invalid) | ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3]))))
             --------------1--------------   ------------------------------------2-----------------------------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT39,T40,T78
10CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Invalid)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       145
 SUB-EXPRESSION ((read_buf[3].attr == Valid) & read_buf[3].err & ((~buf_dependency[3])))
                 -------------1-------------   -------2-------   -----------3----------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T5
110Not Covered
111CoveredT39,T40,T78 

 LINE       145
 SUB-EXPRESSION (read_buf[3].attr == Valid)
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       153
 EXPRESSION (buf_invalid[1] & ((~|buf_invalid[0])))
             -------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       153
 EXPRESSION (buf_invalid[2] & ((~|buf_invalid[(2 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       153
 EXPRESSION (buf_invalid[3] & ((~|buf_invalid[(3 - 1):0])))
             -------1------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       166
 EXPRESSION ((((|buf_invalid_alloc)) | all_buf_dependency) ? '0 : ((buf_valid & (~buf_dependency))))
             ----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       166
 SUB-EXPRESSION (((|buf_invalid_alloc)) | all_buf_dependency)
                 -----------1----------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T5
01Not Covered
10CoveredT1,T2,T3 

 LINE       166
 EXPRESSION (req_o & no_match)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3 

 LINE       185
 EXPRESSION (((|buf_invalid_alloc)) ? buf_invalid_alloc : buf_valid_alloc)
             -----------1----------
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[0].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[1].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[2].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       192
 EXPRESSION (read_buf[3].part == part_i)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[0].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[1].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[2].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       193
 EXPRESSION (read_buf[3].info_sel == info_sel_i)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[0] | buf_wip[0]) & 
      4  (read_buf[0].addr == flash_word_addr) & 
      5  ((~read_buf[0].err)) & 
      6  gen_buf_match[0].part_match & 
      7  gen_buf_match[0].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T5
1011111Not Covered
1101111CoveredT5,T23,T31
1110111CoveredT1,T2,T5
1111011CoveredT39,T40,T78
1111101Not Covered
1111110CoveredT7,T206,T210
1111111CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (buf_valid[0] | buf_wip[0])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[1] | buf_wip[1]) & 
      4  (read_buf[1].addr == flash_word_addr) & 
      5  ((~read_buf[1].err)) & 
      6  gen_buf_match[1].part_match & 
      7  gen_buf_match[1].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T5
1011111Not Covered
1101111CoveredT5,T23,T31
1110111CoveredT1,T2,T5
1111011CoveredT39,T40,T78
1111101Not Covered
1111110CoveredT39,T205,T82
1111111CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (buf_valid[1] | buf_wip[1])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[2] | buf_wip[2]) & 
      4  (read_buf[2].addr == flash_word_addr) & 
      5  ((~read_buf[2].err)) & 
      6  gen_buf_match[2].part_match & 
      7  gen_buf_match[2].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T5
1011111Not Covered
1101111CoveredT5,T23,T31
1110111CoveredT1,T2,T5
1111011CoveredT39,T40,T78
1111101CoveredT203,T204
1111110CoveredT75,T205,T206
1111111CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (buf_valid[2] | buf_wip[2])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       195
 EXPRESSION 
 Number  Term
      1  req_i & 
      2  buf_en_q & 
      3  (buf_valid[3] | buf_wip[3]) & 
      4  (read_buf[3].addr == flash_word_addr) & 
      5  ((~read_buf[3].err)) & 
      6  gen_buf_match[3].part_match & 
      7  gen_buf_match[3].info_sel_match)
-1--2--3--4--5--6--7-StatusTests
0111111CoveredT1,T2,T5
1011111Not Covered
1101111CoveredT5,T23,T31
1110111CoveredT1,T2,T5
1111011CoveredT39,T40,T81
1111101Not Covered
1111110CoveredT7,T81,T213
1111111CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (buf_valid[3] | buf_wip[3])
                 ------1-----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T5 

 LINE       195
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[0].addr == flash_word_addr) & gen_buf_match[0].part_match & gen_buf_match[0].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T206,T210
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[0].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[1].addr == flash_word_addr) & gen_buf_match[1].part_match & gen_buf_match[1].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT39,T205,T82
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[1].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[2].addr == flash_word_addr) & gen_buf_match[2].part_match & gen_buf_match[2].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT75,T205,T206
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[2].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       211
 EXPRESSION ((read_buf[3].addr == flash_word_addr) & gen_buf_match[3].part_match & gen_buf_match[3].info_sel_match)
             ------------------1------------------   -------------2-------------   ---------------3---------------
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T81,T213
111CoveredT1,T2,T3 

 LINE       211
 SUB-EXPRESSION (read_buf[3].addr == flash_word_addr)
                ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[0].part_match & 
      3  gen_buf_match[0].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T88
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[0].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[1].part_match & 
      3  gen_buf_match[1].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT27,T39,T68
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[1].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[2].part_match & 
      3  gen_buf_match[2].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T75
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[2].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       217
 EXPRESSION 
 Number  Term
      1  (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW]) & 
      2  gen_buf_match[3].part_match & 
      3  gen_buf_match[3].info_sel_match)
-1--2--3-StatusTests
011CoveredT1,T2,T4
101CoveredT1,T2,T3
110CoveredT7,T27,T205
111CoveredT1,T2,T3 

 LINE       217
 SUB-EXPRESSION (read_buf[3].addr[flash_phy_pkg::WordW+:flash_phy_pkg::PageW] == addr_i[flash_phy_pkg::BusWordW+:flash_phy_pkg::PageW])
                -----------------------------------------------------------1-----------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       221
 EXPRESSION (buf_valid[0] & (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT5,T13,T31
10CoveredT1,T2,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[0].word_addr_match) | (pg_erase_i & gen_buf_match[0].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T13,T31
010CoveredT5,T13,T31
100CoveredT13,T32,T94 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[0].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[0].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT5,T13,T31 

 LINE       221
 EXPRESSION (buf_valid[1] & (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT5,T13,T31
10CoveredT1,T2,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[1].word_addr_match) | (pg_erase_i & gen_buf_match[1].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T13,T31
010CoveredT5,T13,T31
100CoveredT13,T32,T94 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[1].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[1].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT5,T13,T31 

 LINE       221
 EXPRESSION (buf_valid[2] & (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT5,T13,T31
10CoveredT1,T2,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[2].word_addr_match) | (pg_erase_i & gen_buf_match[2].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T13,T31
010CoveredT5,T13,T31
100CoveredT13,T32,T94 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[2].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[2].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT5,T13,T31 

 LINE       221
 EXPRESSION (buf_valid[3] & (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match)))
             ------1-----   ------------------------------------------------------2-----------------------------------------------------
-1--2-StatusTests
01CoveredT5,T13,T31
10CoveredT1,T2,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (bk_erase_i | (prog_i & gen_buf_match[3].word_addr_match) | (pg_erase_i & gen_buf_match[3].page_addr_match))
                 -----1----   ---------------------2---------------------   -----------------------3-----------------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT5,T13,T31
010CoveredT5,T13,T31
100CoveredT13,T32,T94 

 LINE       221
 SUB-EXPRESSION (prog_i & gen_buf_match[3].word_addr_match)
                 ---1--   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT5,T13,T31 

 LINE       221
 SUB-EXPRESSION (pg_erase_i & gen_buf_match[3].page_addr_match)
                 -----1----   ----------------2---------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T5
11CoveredT5,T13,T31 

 LINE       231
 EXPRESSION (no_match ? (({flash_phy_pkg::NumBuf {(req_i & buf_en_q)}} & buf_alloc)) : '0)
             ----1---
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       238
 EXPRESSION (rdy_o & alloc[0])
             --1--   ----2---
-1--2-StatusTests
01CoveredT39,T75,T76
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       238
 EXPRESSION (rdy_o & alloc[1])
             --1--   ----2---
-1--2-StatusTests
01CoveredT39,T75,T84
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       238
 EXPRESSION (rdy_o & alloc[2])
             --1--   ----2---
-1--2-StatusTests
01CoveredT39,T75,T76
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       238
 EXPRESSION (rdy_o & alloc[3])
             --1--   ----2---
-1--2-StatusTests
01CoveredT39,T75,T76
10CoveredT1,T2,T3
11CoveredT1,T2,T5 

 LINE       289
 EXPRESSION (rd_busy & done_i)
             ---1---   ---2--
-1--2-StatusTests
01CoveredT1,T2,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       296
 EXPRESSION (((|alloc)) ? buf_alloc : buf_match)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       299
 EXPRESSION (req_i && rdy_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T8,T27
11CoveredT1,T2,T3 

 LINE       302
 EXPRESSION (rsp_fifo_vld & data_valid_o)
             ------1-----   ------2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       358
 EXPRESSION (req_o && ack_i)
             --1--    --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT75,T76,T28
11CoveredT1,T2,T3 

 LINE       371
 EXPRESSION (((~rd_busy)) | rd_done)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3 

 LINE       376
 EXPRESSION (rsp_fifo_rdy & scramble_stage_rdy)
             ------1-----   ---------2--------
-1--2-StatusTests
01CoveredT6,T8,T27
10CoveredT18,T19,T137
11CoveredT1,T2,T3 

 LINE       387
 EXPRESSION (buf_en_q == buf_en_i)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       393
 EXPRESSION ((no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy) & ((~all_buf_dependency)) & no_buf_en_change)
             --------------------------------1-------------------------------   -----------2-----------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3 

 LINE       393
 SUB-EXPRESSION (no_match ? (ack_i & flash_rdy & rd_stages_rdy) : rd_stages_rdy)
                 ----1---
-1-StatusTests
0CoveredT1,T2,T5
1CoveredT1,T2,T3 

 LINE       393
 SUB-EXPRESSION (ack_i & flash_rdy & rd_stages_rdy)
                 --1--   ----2----   ------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT6,T8,T27
111CoveredT1,T2,T3 

 LINE       398
 EXPRESSION (req_i & no_buf_en_change & flash_rdy & rd_stages_rdy & no_match)
             --1--   --------2-------   ----3----   ------4------   ----5---
-1--2--3--4--5-StatusTests
01111CoveredT1,T2,T3
10111CoveredT182
11011CoveredT7,T8,T27
11101Not Covered
11110CoveredT1,T2,T5
11111CoveredT1,T2,T3 

 LINE       416
 EXPRESSION (rd_done && rd_attrs.ecc)
             ---1---    ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T13,T6
11CoveredT1,T2,T3 

 LINE       420
 EXPRESSION (rd_done & (data_i == {flash_phy_pkg::FullDataWidth {1'b1}}))
             ---1---   ------------------------2------------------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT7,T46,T75 

 LINE       420
 SUB-EXPRESSION (data_i == {flash_phy_pkg::FullDataWidth {1'b1}})
                ------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       430
 EXPRESSION (valid_ecc & ecc_multi_err)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT4,T13,T44
10CoveredT1,T2,T3
11CoveredT39,T40,T78 

 LINE       439
 EXPRESSION ((data_err | ecc_single_err_o) ? data_ecc_chk : data_i[(flash_phy_pkg::PlainDataWidth - 1):0])
             --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T27,T39 

 LINE       439
 SUB-EXPRESSION (data_err | ecc_single_err_o)
                 ----1---   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T27,T39
10CoveredT39,T40,T78 

 LINE       444
 EXPRESSION (valid_ecc & ecc_single_err)
             ----1----   -------2------
-1--2-StatusTests
01CoveredT4,T13,T8
10CoveredT1,T2,T3
11CoveredT8,T27,T39 

 LINE       469
 EXPRESSION (data_fifo_rdy & mask_fifo_rdy)
             ------1------   ------2------
-1--2-StatusTests
01CoveredT18,T19,T137
10Not Covered
11CoveredT1,T2,T3 

 LINE       475
 EXPRESSION (hint_descram ? (descramble_req_o & descramble_ack_i) : fifo_data_valid)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       475
 SUB-EXPRESSION (descramble_req_o & descramble_ack_i)
                 --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       479
 EXPRESSION (rd_done & rd_attrs.descramble & ((~data_erased)))
             ---1---   ---------2---------   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T13,T6
110CoveredT84,T207,T169
111CoveredT1,T2,T3 

 LINE       483
 EXPRESSION (rd_done & ((~descram)) & ((~fifo_data_valid)))
             ---1---   ------2-----   ----------3---------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT69,T82,T216
111CoveredT1,T13,T6 

 LINE       500
 EXPRESSION (hint_forward & fifo_data_valid)
             ------1-----   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T13,T6 

 LINE       504
 EXPRESSION (fifo_data_ready | fifo_forward_pop)
             -------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3 

 LINE       507
 EXPRESSION (fifo_data_valid & descram_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T13,T6
11CoveredT1,T2,T3 

 LINE       508
 EXPRESSION (fifo_data_valid & forward_q)
             -------1-------   ----2----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T13,T6 

 LINE       539
 EXPRESSION (calc_req_o & calc_ack_i)
             -----1----   -----2----
-1--2-StatusTests
01UnreachableT5,T13,T31
10CoveredT1,T2,T3
11UnreachableT1,T2,T3 

 LINE       564
 EXPRESSION (req_o && ack_i && descramble_i)
             --1--    --2--    ------3-----
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT76,T41,T78
110CoveredT1,T13,T6
111CoveredT1,T2,T3 

 LINE       566
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----
-1--2-StatusTests
01UnreachableT5,T13,T31
10CoveredT1,T2,T3
11UnreachableT1,T2,T3 

 LINE       576
 EXPRESSION (fifo_data_valid & mask_valid & hint_descram)
             -------1-------   -----2----   ------3-----
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT84,T207,T169
111CoveredT1,T2,T3 

 LINE       586
 EXPRESSION 
 Number  Term
      1  forward ? data_int : (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       586
 SUB-EXPRESSION (hint_descram ? ({fifo_data[(flash_phy_pkg::PlainDataWidth - 1)-:flash_phy_pkg::PlainIntgWidth], (descrambled_data_i ^ mask)}) : fifo_data)
                 ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       590
 EXPRESSION (forward ? data_err : (((~hint_forward)) ? data_err_q : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       590
 SUB-EXPRESSION (((~hint_forward)) ? data_err_q : '0)
                 --------1--------
-1-StatusTests
0CoveredT1,T13,T6
1CoveredT1,T2,T3 

 LINE       598
 EXPRESSION (forward | (((~hint_forward)) & fifo_data_ready))
             ---1---   ------------------2------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T13,T6 

 LINE       598
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT1,T13,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       615
 EXPRESSION (forward ? alloc_q : ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0))
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T13,T6 

 LINE       615
 SUB-EXPRESSION ((((~hint_forward)) & fifo_data_ready) ? alloc_q2 : '0)
                 ------------------1------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       615
 SUB-EXPRESSION (((~hint_forward)) & fifo_data_ready)
                 --------1--------   -------2-------
-1--2-StatusTests
01CoveredT1,T13,T6
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       620
 EXPRESSION (rsp_fifo_vld & data_valid & (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update)))
             ------1-----   -----2----   --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT18,T19,T137
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3 

 LINE       620
 SUB-EXPRESSION (((~buf_en_q)) | (rsp_fifo_rdata.buf_sel == update))
                 ------1------   -----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T3
10Not Covered 

 LINE       620
 SUB-EXPRESSION (rsp_fifo_rdata.buf_sel == update)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[0] & buf_valid[0])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T5
1110CoveredT1,T2,T5
1111CoveredT1,T2,T5 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[1] & buf_valid[1])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T5
1110CoveredT1,T2,T5
1111CoveredT1,T2,T5 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[2] & buf_valid[2])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T5
1110CoveredT1,T2,T5
1111CoveredT1,T2,T5 

 LINE       625
 EXPRESSION (buf_en_q & rsp_fifo_vld & rsp_fifo_rdata.buf_sel[3] & buf_valid[3])
             ----1---   ------2-----   ------------3------------   ------4-----
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT1,T2,T5
1110CoveredT1,T2,T5
1111CoveredT1,T2,T5 

 LINE       636
 EXPRESSION (buf_rsp_err | read_buf[i].err)
             -----1-----   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T5
01Not Covered
10Not Covered 

 LINE       642
 EXPRESSION (((|buf_rsp_match)) ? buf_rsp_data : muxed_data)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T5 

 LINE       655
 EXPRESSION (data_err_o ? ({flash_phy_pkg::BusWidth {1'b1}}) : gen_rd.bus_words_packed[rsp_fifo_rdata.word_sel])
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT49,T39,T164 

 LINE       676
 EXPRESSION (rsp_fifo_rdata.intg_ecc_en ? (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth]) : '0)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       676
 SUB-EXPRESSION (truncated_intg != data_out_muxed[flash_phy_pkg::DataWidth+:flash_phy_pkg::PlainIntgWidth])
                ---------------------------------------------1---------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       688
 EXPRESSION (flash_rsp_match | ((|buf_rsp_match)))
             -------1-------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T5
10CoveredT1,T2,T3 

 LINE       691
 EXPRESSION ((data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))) | arb_err_i)
             --------------------------------------1-------------------------------------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT49,T39,T164 

 LINE       691
 SUB-EXPRESSION (data_valid_o & (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err)))
                 ------1-----   -----------------------------2-----------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT49,T39,T164 

 LINE       691
 SUB-EXPRESSION (muxed_err | intg_err | (((|buf_rsp_match)) & buf_rsp_err))
                 ----1----   ----2---   -----------------3----------------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT1,T2,T3
100CoveredT39,T40,T78 

 LINE       691
 SUB-EXPRESSION (((|buf_rsp_match)) & buf_rsp_err)
                 ---------1--------   -----2-----
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T5
11Not Covered 

 LINE       695
 EXPRESSION (data_valid_o & intg_err)
             ------1-----   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT49,T39,T164
Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
Line No.TotalCoveredPercent
Branches 39 39 100.00
TERNARY 185 2 2 100.00
TERNARY 231 2 2 100.00
TERNARY 296 2 2 100.00
TERNARY 439 2 2 100.00
TERNARY 475 2 2 100.00
TERNARY 586 3 3 100.00
TERNARY 590 3 3 100.00
TERNARY 615 3 3 100.00
TERNARY 642 2 2 100.00
TERNARY 676 2 2 100.00
TERNARY 655 2 2 100.00
TERNARY 166 2 2 100.00
IF 256 3 3 100.00
IF 354 4 4 100.00
IF 562 3 3 100.00
IF 634 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	185	((|buf_invalid_alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5 



	LineNo.	Expression
-1-:	231	(no_match) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5 



	LineNo.	Expression
-1-:	296	((|alloc)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	439	((data_err | ecc_single_err_o)) ?

Branches:
-1-StatusTests
1 Covered T8,T27,T39
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	475	(hint_descram) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	586	(forward) ? 
-2-:	586	(hint_descram) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T13,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	590	(forward) ? 
-2-:	590	((~hint_forward)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T13,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T13,T6 



	LineNo.	Expression
-1-:	615	(forward) ? 
-2-:	615	(((~hint_forward) & fifo_data_ready)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T13,T6
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	642	((|buf_rsp_match)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	676	(rsp_fifo_rdata.intg_ecc_en) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	655	(data_err_o) ?

Branches:
-1-StatusTests
1 Covered T49,T39,T164
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	166	(((|buf_invalid_alloc) | all_buf_dependency)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5 



	LineNo.	Expression
-1-:	256	if ((!rst_ni))
-2-:	258	if (idle_o)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	354	if ((!rst_ni))
-2-:	358	if ((req_o && ack_i))
-3-:	365	if (rd_done)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	562	if ((!rst_ni))
-2-:	564	if (((req_o && ack_i) && descramble_i))
-3-:	566	if ((calc_req_o && calc_ack_i))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Unreachable T1,T2,T3
0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	634	if (buf_rsp_match[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T5
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BufferMatchEcc_A 391701045 546074 0 0
ExclusiveOps_A 391701045 390918295 0 0
ExclusiveProgHazard_A 391701045 390918295 0 0
ExclusiveState_A 391701045 390918295 0 0
ForwardCheck_A 391701045 2179385 0 0
IdleCheck_A 391701045 53352682 0 0
MaxBufs_A 1058 1058 0 0
OneHotAlloc_A 391701045 390918295 0 0
OneHotMatch_A 391701045 390918295 0 0
OneHotRspMatch_A 391701045 390918295 0 0
OneHotUpdate_A 391701045 390918295 0 0


BufferMatchEcc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 546074 0 0
T1 3608 7 0 0
T2 115039 256 0 0
T3 3380 0 0 0
T4 541326 0 0 0
T5 165619 1640 0 0
T6 0 201 0 0
T7 0 1244 0 0
T8 0 1856 0 0
T12 1050 0 0 0
T13 108563 4096 0 0
T20 2983 0 0 0
T21 1522 0 0 0
T22 2519 0 0 0
T23 0 39 0 0
T27 0 1047 0 0
T31 0 3084 0 0

ExclusiveOps_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

ExclusiveProgHazard_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

ExclusiveState_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

ForwardCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 2179385 0 0
T1 3608 9 0 0
T2 115039 0 0 0
T3 3380 0 0 0
T4 541326 0 0 0
T5 165619 0 0 0
T6 0 225 0 0
T7 0 9969 0 0
T12 1050 0 0 0
T13 108563 4096 0 0
T20 2983 0 0 0
T21 1522 0 0 0
T22 2519 0 0 0
T23 0 44 0 0
T25 0 1085 0 0
T27 0 355 0 0
T44 0 12382 0 0
T45 0 2 0 0
T46 0 543 0 0

IdleCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 53352682 0 0
T1 3608 153 0 0
T2 115039 1408 0 0
T3 3380 654 0 0
T4 541326 1696 0 0
T5 165619 24520 0 0
T12 1050 132 0 0
T13 108563 107353 0 0
T20 2983 128 0 0
T21 1522 128 0 0
T22 2519 128 0 0

MaxBufs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1058 1058 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T20 1 1 0 0
T21 1 1 0 0
T22 1 1 0 0

OneHotAlloc_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

OneHotMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

OneHotRspMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

OneHotUpdate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 391701045 390918295 0 0
T1 3608 3550 0 0
T2 115039 114940 0 0
T3 3380 2749 0 0
T4 541326 541317 0 0
T5 165619 155647 0 0
T12 1050 958 0 0
T13 108563 108560 0 0
T20 2983 2926 0 0
T21 1522 1457 0 0
T22 2519 2446 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%