T1030 |
/workspace/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2305007956 |
|
|
Dec 27 01:35:57 PM PST 23 |
Dec 27 01:44:51 PM PST 23 |
194607464600 ps |
T1031 |
/workspace/coverage/default/36.flash_ctrl_intr_rd_slow_flash.2846459712 |
|
|
Dec 27 01:38:29 PM PST 23 |
Dec 27 01:41:31 PM PST 23 |
35334710600 ps |
T1032 |
/workspace/coverage/default/3.flash_ctrl_error_mp.3796136424 |
|
|
Dec 27 01:36:07 PM PST 23 |
Dec 27 02:12:44 PM PST 23 |
6086981100 ps |
T1033 |
/workspace/coverage/default/32.flash_ctrl_disable.114614658 |
|
|
Dec 27 01:38:26 PM PST 23 |
Dec 27 01:38:51 PM PST 23 |
12481100 ps |
T1034 |
/workspace/coverage/default/4.flash_ctrl_phy_arb.3300904479 |
|
|
Dec 27 01:36:10 PM PST 23 |
Dec 27 01:45:48 PM PST 23 |
6585209800 ps |
T1035 |
/workspace/coverage/default/19.flash_ctrl_connect.1020403174 |
|
|
Dec 27 01:37:54 PM PST 23 |
Dec 27 01:38:11 PM PST 23 |
52849700 ps |
T1036 |
/workspace/coverage/default/23.flash_ctrl_connect.1204677643 |
|
|
Dec 27 01:37:57 PM PST 23 |
Dec 27 01:38:16 PM PST 23 |
26944500 ps |
T1037 |
/workspace/coverage/default/28.flash_ctrl_intr_rd.3139714954 |
|
|
Dec 27 01:38:35 PM PST 23 |
Dec 27 01:41:28 PM PST 23 |
2794535800 ps |
T1038 |
/workspace/coverage/default/15.flash_ctrl_hw_read_seed_err.3491989031 |
|
|
Dec 27 01:37:59 PM PST 23 |
Dec 27 01:38:15 PM PST 23 |
15086400 ps |
T1039 |
/workspace/coverage/default/13.flash_ctrl_rand_ops.1567779107 |
|
|
Dec 27 01:37:22 PM PST 23 |
Dec 27 01:42:43 PM PST 23 |
2774060100 ps |
T1040 |
/workspace/coverage/default/43.flash_ctrl_disable.2607507096 |
|
|
Dec 27 01:38:41 PM PST 23 |
Dec 27 01:39:04 PM PST 23 |
13351100 ps |
T1041 |
/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.339224497 |
|
|
Dec 27 01:35:49 PM PST 23 |
Dec 27 01:37:22 PM PST 23 |
10020783900 ps |
T1042 |
/workspace/coverage/default/26.flash_ctrl_otp_reset.151474623 |
|
|
Dec 27 01:38:35 PM PST 23 |
Dec 27 01:40:26 PM PST 23 |
35544600 ps |
T1043 |
/workspace/coverage/default/14.flash_ctrl_mp_regions.2621819147 |
|
|
Dec 27 01:37:51 PM PST 23 |
Dec 27 01:51:02 PM PST 23 |
10381229700 ps |
T1044 |
/workspace/coverage/default/75.flash_ctrl_connect.62473869 |
|
|
Dec 27 01:38:45 PM PST 23 |
Dec 27 01:38:59 PM PST 23 |
17573900 ps |
T1045 |
/workspace/coverage/default/23.flash_ctrl_rw_evict_all_en.2545000943 |
|
|
Dec 27 01:37:55 PM PST 23 |
Dec 27 01:38:30 PM PST 23 |
52648400 ps |
T1046 |
/workspace/coverage/default/5.flash_ctrl_fetch_code.232724044 |
|
|
Dec 27 01:35:40 PM PST 23 |
Dec 27 01:36:09 PM PST 23 |
941378300 ps |
T1047 |
/workspace/coverage/default/1.flash_ctrl_rw.611800829 |
|
|
Dec 27 01:33:49 PM PST 23 |
Dec 27 01:42:35 PM PST 23 |
3732092500 ps |
T1048 |
/workspace/coverage/default/2.flash_ctrl_sec_info_access.1449618040 |
|
|
Dec 27 01:35:58 PM PST 23 |
Dec 27 01:37:09 PM PST 23 |
8589830300 ps |
T1049 |
/workspace/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3632806380 |
|
|
Dec 27 01:37:31 PM PST 23 |
Dec 27 01:39:28 PM PST 23 |
10011957800 ps |
T1050 |
/workspace/coverage/default/7.flash_ctrl_ro_derr.1722998543 |
|
|
Dec 27 01:36:21 PM PST 23 |
Dec 27 01:38:47 PM PST 23 |
1660867700 ps |
T1051 |
/workspace/coverage/default/34.flash_ctrl_hw_sec_otp.3880288797 |
|
|
Dec 27 01:38:34 PM PST 23 |
Dec 27 01:40:33 PM PST 23 |
3401170300 ps |
T375 |
/workspace/coverage/default/16.flash_ctrl_invalid_op.1815156917 |
|
|
Dec 27 01:37:57 PM PST 23 |
Dec 27 01:39:26 PM PST 23 |
6028910300 ps |
T1052 |
/workspace/coverage/default/13.flash_ctrl_connect.1085860086 |
|
|
Dec 27 01:37:11 PM PST 23 |
Dec 27 01:37:28 PM PST 23 |
19268300 ps |
T1053 |
/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.3971575978 |
|
|
Dec 27 01:38:34 PM PST 23 |
Dec 27 01:39:06 PM PST 23 |
49348200 ps |
T1054 |
/workspace/coverage/default/1.flash_ctrl_rd_intg.3236505782 |
|
|
Dec 27 01:34:28 PM PST 23 |
Dec 27 01:35:01 PM PST 23 |
613825200 ps |
T1055 |
/workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.1277005082 |
|
|
Dec 27 01:36:17 PM PST 23 |
Dec 27 01:36:31 PM PST 23 |
45786500 ps |
T1056 |
/workspace/coverage/default/12.flash_ctrl_smoke.2774946484 |
|
|
Dec 27 01:37:22 PM PST 23 |
Dec 27 01:40:10 PM PST 23 |
409049000 ps |
T16 |
/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.3941713988 |
|
|
Dec 27 01:35:50 PM PST 23 |
Dec 27 01:36:05 PM PST 23 |
44954800 ps |
T1057 |
/workspace/coverage/default/4.flash_ctrl_smoke.3637961338 |
|
|
Dec 27 01:35:56 PM PST 23 |
Dec 27 01:36:49 PM PST 23 |
130649200 ps |
T1058 |
/workspace/coverage/default/28.flash_ctrl_hw_sec_otp.2249941066 |
|
|
Dec 27 01:38:25 PM PST 23 |
Dec 27 01:39:45 PM PST 23 |
12699528600 ps |
T1059 |
/workspace/coverage/default/13.flash_ctrl_invalid_op.705456327 |
|
|
Dec 27 01:37:40 PM PST 23 |
Dec 27 01:39:12 PM PST 23 |
2094820800 ps |
T1060 |
/workspace/coverage/default/8.flash_ctrl_re_evict.3173644227 |
|
|
Dec 27 01:37:02 PM PST 23 |
Dec 27 01:37:35 PM PST 23 |
46916700 ps |
T1061 |
/workspace/coverage/default/11.flash_ctrl_otp_reset.812488600 |
|
|
Dec 27 01:36:58 PM PST 23 |
Dec 27 01:39:12 PM PST 23 |
77765100 ps |
T1062 |
/workspace/coverage/default/7.flash_ctrl_sec_info_access.3792070597 |
|
|
Dec 27 01:36:21 PM PST 23 |
Dec 27 01:37:39 PM PST 23 |
4828080400 ps |
T1063 |
/workspace/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3392690802 |
|
|
Dec 27 01:35:48 PM PST 23 |
Dec 27 01:39:19 PM PST 23 |
74034050900 ps |
T1064 |
/workspace/coverage/default/2.flash_ctrl_disable.2197361921 |
|
|
Dec 27 01:35:59 PM PST 23 |
Dec 27 01:36:20 PM PST 23 |
11483700 ps |
T1065 |
/workspace/coverage/default/63.flash_ctrl_connect.3242061760 |
|
|
Dec 27 01:38:46 PM PST 23 |
Dec 27 01:39:03 PM PST 23 |
16750200 ps |
T1066 |
/workspace/coverage/default/2.flash_ctrl_config_regwen.1290599983 |
|
|
Dec 27 01:34:36 PM PST 23 |
Dec 27 01:34:51 PM PST 23 |
56990500 ps |
T1067 |
/workspace/coverage/default/15.flash_ctrl_alert_test.1739414343 |
|
|
Dec 27 01:38:05 PM PST 23 |
Dec 27 01:38:20 PM PST 23 |
76381300 ps |
T1068 |
/workspace/coverage/default/11.flash_ctrl_intr_rd.3593412070 |
|
|
Dec 27 01:36:52 PM PST 23 |
Dec 27 01:39:41 PM PST 23 |
1239111500 ps |
T1069 |
/workspace/coverage/default/47.flash_ctrl_otp_reset.2325377231 |
|
|
Dec 27 01:38:38 PM PST 23 |
Dec 27 01:40:53 PM PST 23 |
69877500 ps |
T1070 |
/workspace/coverage/default/62.flash_ctrl_otp_reset.118196604 |
|
|
Dec 27 01:38:45 PM PST 23 |
Dec 27 01:40:58 PM PST 23 |
129702600 ps |
T1071 |
/workspace/coverage/default/18.flash_ctrl_rw_evict_all_en.435448657 |
|
|
Dec 27 01:37:41 PM PST 23 |
Dec 27 01:38:19 PM PST 23 |
63841800 ps |
T1072 |
/workspace/coverage/default/57.flash_ctrl_connect.2936791265 |
|
|
Dec 27 01:38:41 PM PST 23 |
Dec 27 01:38:58 PM PST 23 |
14222100 ps |
T1073 |
/workspace/coverage/default/29.flash_ctrl_rw_evict.2715183836 |
|
|
Dec 27 01:38:22 PM PST 23 |
Dec 27 01:38:54 PM PST 23 |
36856000 ps |
T1074 |
/workspace/coverage/default/2.flash_ctrl_derr_detect.36733063 |
|
|
Dec 27 01:34:35 PM PST 23 |
Dec 27 01:36:19 PM PST 23 |
201299700 ps |
T1075 |
/workspace/coverage/default/4.flash_ctrl_stress_all.3694068755 |
|
|
Dec 27 01:35:01 PM PST 23 |
Dec 27 02:08:09 PM PST 23 |
951946800 ps |
T1076 |
/workspace/coverage/default/0.flash_ctrl_rd_buff_evict.552189440 |
|
|
Dec 27 01:33:58 PM PST 23 |
Dec 27 01:36:32 PM PST 23 |
2816104700 ps |
T1077 |
/workspace/coverage/default/39.flash_ctrl_intr_rd_slow_flash.701782312 |
|
|
Dec 27 01:38:39 PM PST 23 |
Dec 27 01:41:51 PM PST 23 |
8132358300 ps |
T222 |
/workspace/coverage/default/57.flash_ctrl_otp_reset.3018689952 |
|
|
Dec 27 01:38:40 PM PST 23 |
Dec 27 01:40:54 PM PST 23 |
39766600 ps |
T1078 |
/workspace/coverage/default/19.flash_ctrl_ro.2831750434 |
|
|
Dec 27 01:37:39 PM PST 23 |
Dec 27 01:39:35 PM PST 23 |
950037300 ps |
T1079 |
/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1484735344 |
|
|
Dec 27 01:39:38 PM PST 23 |
Dec 27 01:39:52 PM PST 23 |
26581800 ps |
T1080 |
/workspace/coverage/default/62.flash_ctrl_connect.820165525 |
|
|
Dec 27 01:39:00 PM PST 23 |
Dec 27 01:39:14 PM PST 23 |
18391700 ps |
T1081 |
/workspace/coverage/default/14.flash_ctrl_alert_test.1001902623 |
|
|
Dec 27 01:37:37 PM PST 23 |
Dec 27 01:37:58 PM PST 23 |
65970300 ps |
T1082 |
/workspace/coverage/default/61.flash_ctrl_connect.1431156954 |
|
|
Dec 27 01:38:51 PM PST 23 |
Dec 27 01:39:05 PM PST 23 |
14725300 ps |
T1083 |
/workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1113909978 |
|
|
Dec 27 01:36:22 PM PST 23 |
Dec 27 01:37:04 PM PST 23 |
312102300 ps |
T1084 |
/workspace/coverage/default/14.flash_ctrl_ro.730862223 |
|
|
Dec 27 01:37:34 PM PST 23 |
Dec 27 01:39:06 PM PST 23 |
1645387000 ps |
T1085 |
/workspace/coverage/default/42.flash_ctrl_disable.3074462196 |
|
|
Dec 27 01:38:49 PM PST 23 |
Dec 27 01:39:11 PM PST 23 |
37891600 ps |
T1086 |
/workspace/coverage/default/0.flash_ctrl_serr_address.4234048982 |
|
|
Dec 27 01:33:55 PM PST 23 |
Dec 27 01:35:06 PM PST 23 |
1226002500 ps |
T1087 |
/workspace/coverage/default/2.flash_ctrl_intr_wr_slow_flash.3664019439 |
|
|
Dec 27 01:35:01 PM PST 23 |
Dec 27 01:42:36 PM PST 23 |
282413497500 ps |
T227 |
/workspace/coverage/default/17.flash_ctrl_disable.16159585 |
|
|
Dec 27 01:37:55 PM PST 23 |
Dec 27 01:38:20 PM PST 23 |
11063100 ps |
T1088 |
/workspace/coverage/default/1.flash_ctrl_intr_rd.3479569513 |
|
|
Dec 27 01:34:10 PM PST 23 |
Dec 27 01:37:03 PM PST 23 |
16789231600 ps |
T1089 |
/workspace/coverage/default/20.flash_ctrl_sec_info_access.3295259574 |
|
|
Dec 27 01:37:54 PM PST 23 |
Dec 27 01:38:52 PM PST 23 |
353511700 ps |
T1090 |
/workspace/coverage/default/28.flash_ctrl_rw_evict_all_en.604874175 |
|
|
Dec 27 01:38:26 PM PST 23 |
Dec 27 01:39:00 PM PST 23 |
30472600 ps |
T1091 |
/workspace/coverage/default/17.flash_ctrl_hw_sec_otp.4241060783 |
|
|
Dec 27 01:37:54 PM PST 23 |
Dec 27 01:39:17 PM PST 23 |
3366292600 ps |
T1092 |
/workspace/coverage/default/42.flash_ctrl_alert_test.3851234454 |
|
|
Dec 27 01:38:48 PM PST 23 |
Dec 27 01:39:02 PM PST 23 |
30376200 ps |
T1093 |
/workspace/coverage/default/9.flash_ctrl_mp_regions.2358631350 |
|
|
Dec 27 01:37:05 PM PST 23 |
Dec 27 01:44:48 PM PST 23 |
6795395800 ps |
T1094 |
/workspace/coverage/default/3.flash_ctrl_otp_reset.952488967 |
|
|
Dec 27 01:35:57 PM PST 23 |
Dec 27 01:38:09 PM PST 23 |
82257700 ps |
T1095 |
/workspace/coverage/default/0.flash_ctrl_erase_suspend.3366058216 |
|
|
Dec 27 01:33:57 PM PST 23 |
Dec 27 01:42:18 PM PST 23 |
6974034500 ps |
T1096 |
/workspace/coverage/default/7.flash_ctrl_lcmgr_intg.1803795638 |
|
|
Dec 27 01:36:22 PM PST 23 |
Dec 27 01:36:39 PM PST 23 |
34762600 ps |
T1097 |
/workspace/coverage/default/22.flash_ctrl_intr_rd.1851080482 |
|
|
Dec 27 01:37:54 PM PST 23 |
Dec 27 01:41:00 PM PST 23 |
1046656200 ps |
T1098 |
/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.1898561165 |
|
|
Dec 27 01:37:53 PM PST 23 |
Dec 27 01:38:29 PM PST 23 |
39826800 ps |
T1099 |
/workspace/coverage/default/12.flash_ctrl_hw_rma_reset.1966493936 |
|
|
Dec 27 01:37:29 PM PST 23 |
Dec 27 01:49:26 PM PST 23 |
40126908400 ps |
T1100 |
/workspace/coverage/default/33.flash_ctrl_alert_test.275784867 |
|
|
Dec 27 01:38:29 PM PST 23 |
Dec 27 01:38:45 PM PST 23 |
138904300 ps |
T1101 |
/workspace/coverage/default/3.flash_ctrl_wo.1200021044 |
|
|
Dec 27 01:34:35 PM PST 23 |
Dec 27 01:37:58 PM PST 23 |
10825714800 ps |
T1102 |
/workspace/coverage/default/23.flash_ctrl_prog_reset.81477052 |
|
|
Dec 27 01:37:57 PM PST 23 |
Dec 27 01:38:14 PM PST 23 |
243626300 ps |
T1103 |
/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.2127726003 |
|
|
Dec 27 01:38:21 PM PST 23 |
Dec 27 01:41:54 PM PST 23 |
171845435300 ps |
T1104 |
/workspace/coverage/default/8.flash_ctrl_hw_sec_otp.2257402925 |
|
|
Dec 27 01:36:20 PM PST 23 |
Dec 27 01:37:15 PM PST 23 |
1645187000 ps |
T1105 |
/workspace/coverage/default/40.flash_ctrl_connect.3209357377 |
|
|
Dec 27 01:39:01 PM PST 23 |
Dec 27 01:39:15 PM PST 23 |
14591200 ps |
T204 |
/workspace/coverage/default/9.flash_ctrl_rw_serr.1027883625 |
|
|
Dec 27 01:37:10 PM PST 23 |
Dec 27 01:46:24 PM PST 23 |
3562472600 ps |
T1106 |
/workspace/coverage/default/11.flash_ctrl_hw_sec_otp.2020453375 |
|
|
Dec 27 01:37:20 PM PST 23 |
Dec 27 01:38:52 PM PST 23 |
2044350600 ps |
T1107 |
/workspace/coverage/default/0.flash_ctrl_rw_evict.2082974195 |
|
|
Dec 27 01:34:08 PM PST 23 |
Dec 27 01:34:41 PM PST 23 |
346752900 ps |
T1108 |
/workspace/coverage/default/9.flash_ctrl_lcmgr_intg.1379135015 |
|
|
Dec 27 01:36:51 PM PST 23 |
Dec 27 01:37:05 PM PST 23 |
29529800 ps |
T1109 |
/workspace/coverage/default/8.flash_ctrl_rw_evict.287217231 |
|
|
Dec 27 01:36:49 PM PST 23 |
Dec 27 01:37:26 PM PST 23 |
1237436200 ps |
T228 |
/workspace/coverage/default/12.flash_ctrl_disable.2035735718 |
|
|
Dec 27 01:37:09 PM PST 23 |
Dec 27 01:37:32 PM PST 23 |
10714100 ps |
T1110 |
/workspace/coverage/default/13.flash_ctrl_intr_rd.3559858917 |
|
|
Dec 27 01:37:17 PM PST 23 |
Dec 27 01:39:48 PM PST 23 |
2867464500 ps |
T1111 |
/workspace/coverage/default/27.flash_ctrl_sec_info_access.1775993482 |
|
|
Dec 27 01:37:58 PM PST 23 |
Dec 27 01:39:04 PM PST 23 |
4309540400 ps |
T1112 |
/workspace/coverage/default/6.flash_ctrl_prog_reset.475746810 |
|
|
Dec 27 01:36:12 PM PST 23 |
Dec 27 01:36:26 PM PST 23 |
36525200 ps |
T1113 |
/workspace/coverage/default/17.flash_ctrl_phy_arb.1820025186 |
|
|
Dec 27 01:37:54 PM PST 23 |
Dec 27 01:41:11 PM PST 23 |
89628600 ps |
T1114 |
/workspace/coverage/default/19.flash_ctrl_rw.1620808493 |
|
|
Dec 27 01:37:52 PM PST 23 |
Dec 27 01:46:51 PM PST 23 |
7643652500 ps |
T1115 |
/workspace/coverage/default/7.flash_ctrl_rw.4198826652 |
|
|
Dec 27 01:36:02 PM PST 23 |
Dec 27 01:45:36 PM PST 23 |
22490547700 ps |
T1116 |
/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.2879390326 |
|
|
Dec 27 01:38:38 PM PST 23 |
Dec 27 01:39:10 PM PST 23 |
45949300 ps |
T1117 |
/workspace/coverage/default/69.flash_ctrl_otp_reset.2348628640 |
|
|
Dec 27 01:38:44 PM PST 23 |
Dec 27 01:40:56 PM PST 23 |
39831700 ps |
T1118 |
/workspace/coverage/default/4.flash_ctrl_serr_address.2765998111 |
|
|
Dec 27 01:35:02 PM PST 23 |
Dec 27 01:35:54 PM PST 23 |
352238100 ps |
T1119 |
/workspace/coverage/default/3.flash_ctrl_smoke.514939116 |
|
|
Dec 27 01:35:04 PM PST 23 |
Dec 27 01:37:56 PM PST 23 |
132719400 ps |
T1120 |
/workspace/coverage/default/66.flash_ctrl_otp_reset.3158351525 |
|
|
Dec 27 01:38:45 PM PST 23 |
Dec 27 01:41:01 PM PST 23 |
44613400 ps |
T1121 |
/workspace/coverage/default/32.flash_ctrl_connect.3250422272 |
|
|
Dec 27 01:38:32 PM PST 23 |
Dec 27 01:38:49 PM PST 23 |
18784600 ps |
T1122 |
/workspace/coverage/default/58.flash_ctrl_connect.4005339410 |
|
|
Dec 27 01:38:56 PM PST 23 |
Dec 27 01:39:12 PM PST 23 |
16099200 ps |
T1123 |
/workspace/coverage/default/53.flash_ctrl_otp_reset.2512116703 |
|
|
Dec 27 01:38:41 PM PST 23 |
Dec 27 01:40:52 PM PST 23 |
38736400 ps |
T1124 |
/workspace/coverage/default/1.flash_ctrl_otp_reset.3559558712 |
|
|
Dec 27 01:34:06 PM PST 23 |
Dec 27 01:36:19 PM PST 23 |
309844700 ps |
T1125 |
/workspace/coverage/default/38.flash_ctrl_rw_evict.1977197191 |
|
|
Dec 27 01:38:41 PM PST 23 |
Dec 27 01:39:14 PM PST 23 |
32627800 ps |
T1126 |
/workspace/coverage/default/4.flash_ctrl_ro_derr.3666265303 |
|
|
Dec 27 01:35:48 PM PST 23 |
Dec 27 01:38:03 PM PST 23 |
9345016400 ps |
T331 |
/workspace/coverage/default/33.flash_ctrl_disable.861237042 |
|
|
Dec 27 01:38:29 PM PST 23 |
Dec 27 01:38:54 PM PST 23 |
10690500 ps |
T1127 |
/workspace/coverage/default/11.flash_ctrl_smoke.994854331 |
|
|
Dec 27 01:37:26 PM PST 23 |
Dec 27 01:39:03 PM PST 23 |
29722100 ps |
T1128 |
/workspace/coverage/default/11.flash_ctrl_phy_arb.544058047 |
|
|
Dec 27 01:37:21 PM PST 23 |
Dec 27 01:46:32 PM PST 23 |
3166236700 ps |
T1129 |
/workspace/coverage/default/4.flash_ctrl_intr_rd.1501518667 |
|
|
Dec 27 01:35:41 PM PST 23 |
Dec 27 01:38:25 PM PST 23 |
1267264800 ps |
T1130 |
/workspace/coverage/default/8.flash_ctrl_rw_evict_all_en.1563099525 |
|
|
Dec 27 01:36:25 PM PST 23 |
Dec 27 01:36:58 PM PST 23 |
46178800 ps |
T1131 |
/workspace/coverage/default/2.flash_ctrl_hw_read_seed_err.2726155566 |
|
|
Dec 27 01:36:00 PM PST 23 |
Dec 27 01:36:13 PM PST 23 |
25748100 ps |
T1132 |
/workspace/coverage/default/28.flash_ctrl_otp_reset.821287589 |
|
|
Dec 27 01:38:34 PM PST 23 |
Dec 27 01:40:47 PM PST 23 |
53280100 ps |
T1133 |
/workspace/coverage/default/9.flash_ctrl_disable.122522340 |
|
|
Dec 27 01:36:56 PM PST 23 |
Dec 27 01:37:18 PM PST 23 |
34696700 ps |
T1134 |
/workspace/coverage/default/23.flash_ctrl_intr_rd_slow_flash.2740624632 |
|
|
Dec 27 01:37:57 PM PST 23 |
Dec 27 01:41:42 PM PST 23 |
34168212900 ps |
T1135 |
/workspace/coverage/default/4.flash_ctrl_rw_evict_all_en.2788429164 |
|
|
Dec 27 01:36:03 PM PST 23 |
Dec 27 01:36:36 PM PST 23 |
31602200 ps |
T1136 |
/workspace/coverage/default/77.flash_ctrl_connect.2664143084 |
|
|
Dec 27 01:38:44 PM PST 23 |
Dec 27 01:39:00 PM PST 23 |
13965600 ps |
T1137 |
/workspace/coverage/default/17.flash_ctrl_hw_read_seed_err.2828762785 |
|
|
Dec 27 01:39:40 PM PST 23 |
Dec 27 01:39:53 PM PST 23 |
46782000 ps |
T1138 |
/workspace/coverage/default/10.flash_ctrl_rand_ops.1949317128 |
|
|
Dec 27 01:37:19 PM PST 23 |
Dec 27 01:48:48 PM PST 23 |
5798496900 ps |
T1139 |
/workspace/coverage/default/1.flash_ctrl_ro_serr.136479030 |
|
|
Dec 27 01:34:15 PM PST 23 |
Dec 27 01:36:17 PM PST 23 |
2677629200 ps |
T1140 |
/workspace/coverage/default/5.flash_ctrl_error_prog_win.2088925316 |
|
|
Dec 27 01:35:34 PM PST 23 |
Dec 27 01:50:09 PM PST 23 |
1730920500 ps |
T1141 |
/workspace/coverage/default/17.flash_ctrl_wo.867929008 |
|
|
Dec 27 01:37:57 PM PST 23 |
Dec 27 01:40:30 PM PST 23 |
3621194600 ps |
T1142 |
/workspace/coverage/default/2.flash_ctrl_rd_intg.2765249496 |
|
|
Dec 27 01:34:52 PM PST 23 |
Dec 27 01:35:25 PM PST 23 |
316395200 ps |
T1143 |
/workspace/coverage/default/7.flash_ctrl_re_evict.778765906 |
|
|
Dec 27 01:36:21 PM PST 23 |
Dec 27 01:36:58 PM PST 23 |
84842200 ps |
T1144 |
/workspace/coverage/default/19.flash_ctrl_intr_rd.3140426973 |
|
|
Dec 27 01:37:55 PM PST 23 |
Dec 27 01:40:52 PM PST 23 |
5213107700 ps |
T1145 |
/workspace/coverage/default/3.flash_ctrl_intr_wr.3283971831 |
|
|
Dec 27 01:34:59 PM PST 23 |
Dec 27 01:36:55 PM PST 23 |
4034797100 ps |
T1146 |
/workspace/coverage/default/29.flash_ctrl_connect.2802489196 |
|
|
Dec 27 01:38:24 PM PST 23 |
Dec 27 01:38:38 PM PST 23 |
37701200 ps |
T334 |
/workspace/coverage/default/39.flash_ctrl_sec_info_access.3497046129 |
|
|
Dec 27 01:38:41 PM PST 23 |
Dec 27 01:40:14 PM PST 23 |
6960465900 ps |
T1147 |
/workspace/coverage/default/30.flash_ctrl_smoke.2658498347 |
|
|
Dec 27 01:38:19 PM PST 23 |
Dec 27 01:41:31 PM PST 23 |
127020700 ps |
T1148 |
/workspace/coverage/default/18.flash_ctrl_re_evict.2195409408 |
|
|
Dec 27 01:38:06 PM PST 23 |
Dec 27 01:38:47 PM PST 23 |
147189600 ps |
T1149 |
/workspace/coverage/default/25.flash_ctrl_smoke.878128749 |
|
|
Dec 27 01:37:57 PM PST 23 |
Dec 27 01:41:10 PM PST 23 |
176781300 ps |
T1150 |
/workspace/coverage/default/44.flash_ctrl_disable.90186376 |
|
|
Dec 27 01:38:36 PM PST 23 |
Dec 27 01:38:59 PM PST 23 |
12932500 ps |
T1151 |
/workspace/coverage/default/4.flash_ctrl_rw.1289670244 |
|
|
Dec 27 01:35:54 PM PST 23 |
Dec 27 01:43:18 PM PST 23 |
10763099700 ps |
T1152 |
/workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.1734616713 |
|
|
Dec 27 01:38:18 PM PST 23 |
Dec 27 01:38:51 PM PST 23 |
31984700 ps |
T1153 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3051778790 |
|
|
Dec 27 12:50:07 PM PST 23 |
Dec 27 12:50:26 PM PST 23 |
44946400 ps |
T1154 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3485266717 |
|
|
Dec 27 12:49:56 PM PST 23 |
Dec 27 12:50:44 PM PST 23 |
198210900 ps |
T1155 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3381506702 |
|
|
Dec 27 12:49:47 PM PST 23 |
Dec 27 12:50:04 PM PST 23 |
46148900 ps |
T1156 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2936075142 |
|
|
Dec 27 12:50:01 PM PST 23 |
Dec 27 12:50:19 PM PST 23 |
49714400 ps |
T290 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.758937765 |
|
|
Dec 27 12:49:47 PM PST 23 |
Dec 27 12:50:12 PM PST 23 |
211776300 ps |
T1157 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3564073297 |
|
|
Dec 27 12:49:56 PM PST 23 |
Dec 27 12:50:14 PM PST 23 |
11845500 ps |
T392 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1546518298 |
|
|
Dec 27 12:50:33 PM PST 23 |
Dec 27 12:50:56 PM PST 23 |
61300500 ps |
T291 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.187689282 |
|
|
Dec 27 12:50:14 PM PST 23 |
Dec 27 12:50:40 PM PST 23 |
102496600 ps |
T261 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2428786520 |
|
|
Dec 27 12:49:53 PM PST 23 |
Dec 27 01:04:55 PM PST 23 |
1531954400 ps |
T246 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.904335099 |
|
|
Dec 27 12:50:05 PM PST 23 |
Dec 27 12:50:25 PM PST 23 |
16273600 ps |
T1158 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.4274229846 |
|
|
Dec 27 12:50:05 PM PST 23 |
Dec 27 12:50:25 PM PST 23 |
17159900 ps |
T1159 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.251363908 |
|
|
Dec 27 12:49:58 PM PST 23 |
Dec 27 12:50:14 PM PST 23 |
31664200 ps |
T1160 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3238886649 |
|
|
Dec 27 12:49:59 PM PST 23 |
Dec 27 12:50:17 PM PST 23 |
57833700 ps |
T1161 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2522468575 |
|
|
Dec 27 12:49:58 PM PST 23 |
Dec 27 12:50:47 PM PST 23 |
4941896600 ps |
T292 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2321614183 |
|
|
Dec 27 12:49:53 PM PST 23 |
Dec 27 12:57:49 PM PST 23 |
1760912300 ps |
T1162 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.13936309 |
|
|
Dec 27 12:49:57 PM PST 23 |
Dec 27 12:50:34 PM PST 23 |
127411800 ps |
T263 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2965147853 |
|
|
Dec 27 12:49:53 PM PST 23 |
Dec 27 12:50:13 PM PST 23 |
37970300 ps |
T264 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2814258496 |
|
|
Dec 27 12:49:44 PM PST 23 |
Dec 27 12:50:04 PM PST 23 |
49003300 ps |
T1163 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2219207820 |
|
|
Dec 27 12:50:13 PM PST 23 |
Dec 27 12:50:38 PM PST 23 |
139299600 ps |
T323 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.424321371 |
|
|
Dec 27 12:50:12 PM PST 23 |
Dec 27 12:58:00 PM PST 23 |
213989900 ps |
T1164 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.3466564475 |
|
|
Dec 27 12:49:52 PM PST 23 |
Dec 27 12:50:09 PM PST 23 |
29875900 ps |
T1165 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.648943371 |
|
|
Dec 27 12:50:11 PM PST 23 |
Dec 27 12:50:31 PM PST 23 |
68776900 ps |
T1166 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.209020799 |
|
|
Dec 27 12:50:08 PM PST 23 |
Dec 27 12:50:31 PM PST 23 |
14802200 ps |
T1167 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1963430744 |
|
|
Dec 27 12:49:51 PM PST 23 |
Dec 27 12:50:09 PM PST 23 |
136752200 ps |
T1168 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.2000405918 |
|
|
Dec 27 12:49:58 PM PST 23 |
Dec 27 12:50:14 PM PST 23 |
17296700 ps |
T1169 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3790785956 |
|
|
Dec 27 12:49:38 PM PST 23 |
Dec 27 12:49:57 PM PST 23 |
13505300 ps |
T1170 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1035259953 |
|
|
Dec 27 12:50:08 PM PST 23 |
Dec 27 12:50:29 PM PST 23 |
23226100 ps |
T293 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2978894029 |
|
|
Dec 27 12:49:57 PM PST 23 |
Dec 27 01:04:59 PM PST 23 |
802761500 ps |
T1171 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.589497031 |
|
|
Dec 27 12:49:50 PM PST 23 |
Dec 27 12:50:10 PM PST 23 |
22729900 ps |
T1172 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2778086378 |
|
|
Dec 27 12:50:02 PM PST 23 |
Dec 27 12:50:21 PM PST 23 |
15045000 ps |
T1173 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.355987681 |
|
|
Dec 27 12:49:46 PM PST 23 |
Dec 27 12:50:05 PM PST 23 |
31996000 ps |
T1174 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1656491969 |
|
|
Dec 27 12:50:02 PM PST 23 |
Dec 27 12:50:37 PM PST 23 |
484693500 ps |
T318 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.1662475867 |
|
|
Dec 27 12:50:08 PM PST 23 |
Dec 27 01:05:17 PM PST 23 |
4647712800 ps |
T1175 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4124834306 |
|
|
Dec 27 12:49:58 PM PST 23 |
Dec 27 12:50:17 PM PST 23 |
166887200 ps |
T393 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.3845234974 |
|
|
Dec 27 12:49:49 PM PST 23 |
Dec 27 12:50:11 PM PST 23 |
57173500 ps |
T1176 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1413554208 |
|
|
Dec 27 12:49:31 PM PST 23 |
Dec 27 12:50:11 PM PST 23 |
127894900 ps |
T1177 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.3189618192 |
|
|
Dec 27 12:49:56 PM PST 23 |
Dec 27 12:50:12 PM PST 23 |
38972800 ps |
T1178 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1996748995 |
|
|
Dec 27 12:50:10 PM PST 23 |
Dec 27 12:50:29 PM PST 23 |
20510100 ps |
T1179 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.1694207414 |
|
|
Dec 27 12:49:52 PM PST 23 |
Dec 27 12:50:09 PM PST 23 |
36184200 ps |
T1180 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3562353156 |
|
|
Dec 27 12:49:57 PM PST 23 |
Dec 27 12:50:19 PM PST 23 |
96480700 ps |
T1181 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2436213329 |
|
|
Dec 27 12:49:51 PM PST 23 |
Dec 27 12:50:08 PM PST 23 |
56224400 ps |
T1182 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3784296183 |
|
|
Dec 27 12:50:08 PM PST 23 |
Dec 27 12:50:27 PM PST 23 |
30927800 ps |
T1183 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.2128633772 |
|
|
Dec 27 12:49:43 PM PST 23 |
Dec 27 12:50:02 PM PST 23 |
150150700 ps |
T1184 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1290688282 |
|
|
Dec 27 12:50:31 PM PST 23 |
Dec 27 12:50:51 PM PST 23 |
22969000 ps |
T1185 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.591788674 |
|
|
Dec 27 12:50:08 PM PST 23 |
Dec 27 12:50:30 PM PST 23 |
164532000 ps |
T1186 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3863165221 |
|
|
Dec 27 12:50:03 PM PST 23 |
Dec 27 12:50:24 PM PST 23 |
13483400 ps |
T1187 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2385523052 |
|
|
Dec 27 12:50:22 PM PST 23 |
Dec 27 12:50:45 PM PST 23 |
21930600 ps |
T1188 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.3085120758 |
|
|
Dec 27 12:49:37 PM PST 23 |
Dec 27 12:49:54 PM PST 23 |
50183400 ps |
T1189 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.206323203 |
|
|
Dec 27 12:50:00 PM PST 23 |
Dec 27 12:50:18 PM PST 23 |
18641400 ps |
T1190 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1842114433 |
|
|
Dec 27 12:49:48 PM PST 23 |
Dec 27 12:50:08 PM PST 23 |
51759800 ps |
T1191 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.141702116 |
|
|
Dec 27 12:49:55 PM PST 23 |
Dec 27 12:50:14 PM PST 23 |
34515500 ps |
T1192 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1241327149 |
|
|
Dec 27 12:49:53 PM PST 23 |
Dec 27 12:50:43 PM PST 23 |
68187900 ps |
T1193 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.4036581423 |
|
|
Dec 27 12:49:59 PM PST 23 |
Dec 27 12:50:18 PM PST 23 |
20099500 ps |
T1194 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.367244315 |
|
|
Dec 27 12:49:58 PM PST 23 |
Dec 27 12:50:15 PM PST 23 |
15674100 ps |
T1195 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3594350091 |
|
|
Dec 27 12:50:15 PM PST 23 |
Dec 27 12:50:41 PM PST 23 |
205941300 ps |
T1196 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.1510264932 |
|
|
Dec 27 12:50:04 PM PST 23 |
Dec 27 12:50:24 PM PST 23 |
14483800 ps |
T1197 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.917700598 |
|
|
Dec 27 12:50:01 PM PST 23 |
Dec 27 12:50:26 PM PST 23 |
28531500 ps |
T1198 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.688419360 |
|
|
Dec 27 12:49:46 PM PST 23 |
Dec 27 12:50:06 PM PST 23 |
24568000 ps |
T294 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3907472607 |
|
|
Dec 27 12:50:05 PM PST 23 |
Dec 27 12:50:51 PM PST 23 |
1431923500 ps |
T1199 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.348226529 |
|
|
Dec 27 12:49:48 PM PST 23 |
Dec 27 12:50:06 PM PST 23 |
208513300 ps |
T1200 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1973289774 |
|
|
Dec 27 12:50:00 PM PST 23 |
Dec 27 12:50:19 PM PST 23 |
67190800 ps |
T295 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1702183485 |
|
|
Dec 27 12:49:30 PM PST 23 |
Dec 27 12:49:55 PM PST 23 |
834225700 ps |
T1201 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.2706196261 |
|
|
Dec 27 12:49:31 PM PST 23 |
Dec 27 12:49:50 PM PST 23 |
31089400 ps |
T1202 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.463861791 |
|
|
Dec 27 12:49:43 PM PST 23 |
Dec 27 12:50:19 PM PST 23 |
329691300 ps |
T1203 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1846093799 |
|
|
Dec 27 12:50:03 PM PST 23 |
Dec 27 12:50:24 PM PST 23 |
15049200 ps |
T1204 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3044822826 |
|
|
Dec 27 12:49:28 PM PST 23 |
Dec 27 01:04:26 PM PST 23 |
336040600 ps |
T1205 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1591814248 |
|
|
Dec 27 12:50:10 PM PST 23 |
Dec 27 12:50:29 PM PST 23 |
45151100 ps |
T1206 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2782102390 |
|
|
Dec 27 12:49:49 PM PST 23 |
Dec 27 12:50:06 PM PST 23 |
54397900 ps |
T1207 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.943136874 |
|
|
Dec 27 12:50:05 PM PST 23 |
Dec 27 12:50:32 PM PST 23 |
189398900 ps |
T324 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.911523448 |
|
|
Dec 27 12:50:13 PM PST 23 |
Dec 27 12:57:56 PM PST 23 |
910651100 ps |
T1208 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.4185466943 |
|
|
Dec 27 12:49:46 PM PST 23 |
Dec 27 12:50:05 PM PST 23 |
39883600 ps |
T1209 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2378889598 |
|
|
Dec 27 12:49:33 PM PST 23 |
Dec 27 12:49:52 PM PST 23 |
20692200 ps |
T326 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.4077541938 |
|
|
Dec 27 12:49:46 PM PST 23 |
Dec 27 12:57:31 PM PST 23 |
695314400 ps |
T247 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3046456683 |
|
|
Dec 27 12:49:59 PM PST 23 |
Dec 27 12:50:15 PM PST 23 |
59458000 ps |
T1210 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1752280482 |
|
|
Dec 27 12:49:47 PM PST 23 |
Dec 27 12:50:07 PM PST 23 |
19382000 ps |
T248 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.1422326206 |
|
|
Dec 27 12:50:03 PM PST 23 |
Dec 27 12:50:21 PM PST 23 |
27598400 ps |
T1211 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.1594393622 |
|
|
Dec 27 12:49:47 PM PST 23 |
Dec 27 12:50:05 PM PST 23 |
144417800 ps |
T1212 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.180540635 |
|
|
Dec 27 12:50:25 PM PST 23 |
Dec 27 12:50:47 PM PST 23 |
114794700 ps |
T1213 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.2463900430 |
|
|
Dec 27 12:49:50 PM PST 23 |
Dec 27 12:50:07 PM PST 23 |
33620100 ps |
T1214 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2497143139 |
|
|
Dec 27 12:50:00 PM PST 23 |
Dec 27 12:50:20 PM PST 23 |
400106100 ps |
T1215 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3975714323 |
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|
Dec 27 12:50:12 PM PST 23 |
Dec 27 12:50:32 PM PST 23 |
32152100 ps |
T1216 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3116299323 |
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|
Dec 27 12:50:07 PM PST 23 |
Dec 27 12:50:27 PM PST 23 |
29923800 ps |
T260 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2157309365 |
|
|
Dec 27 12:50:07 PM PST 23 |
Dec 27 12:50:31 PM PST 23 |
487702800 ps |
T1217 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.594480392 |
|
|
Dec 27 12:50:02 PM PST 23 |
Dec 27 12:50:25 PM PST 23 |
35923800 ps |
T1218 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.726034834 |
|
|
Dec 27 12:50:25 PM PST 23 |
Dec 27 12:50:45 PM PST 23 |
25107000 ps |
T1219 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.442974692 |
|
|
Dec 27 12:50:20 PM PST 23 |
Dec 27 12:50:42 PM PST 23 |
72506700 ps |
T1220 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2759975729 |
|
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Dec 27 12:49:47 PM PST 23 |
Dec 27 12:50:09 PM PST 23 |
35591000 ps |
T1221 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.4064850343 |
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Dec 27 12:49:59 PM PST 23 |
Dec 27 12:50:19 PM PST 23 |
92632000 ps |
T1222 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3037182564 |
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Dec 27 12:49:56 PM PST 23 |
Dec 27 12:50:11 PM PST 23 |
27436100 ps |
T1223 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2044886371 |
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Dec 27 12:50:24 PM PST 23 |
Dec 27 12:50:47 PM PST 23 |
46213100 ps |
T1224 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1202567666 |
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Dec 27 12:50:01 PM PST 23 |
Dec 27 12:50:21 PM PST 23 |
13623600 ps |
T1225 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.4122262961 |
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Dec 27 12:50:02 PM PST 23 |
Dec 27 12:50:23 PM PST 23 |
19305200 ps |
T1226 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.189042734 |
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Dec 27 12:50:04 PM PST 23 |
Dec 27 12:50:23 PM PST 23 |
17810700 ps |
T1227 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.25419034 |
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Dec 27 12:50:04 PM PST 23 |
Dec 27 12:50:25 PM PST 23 |
134174200 ps |
T1228 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2486256513 |
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Dec 27 12:49:58 PM PST 23 |
Dec 27 12:50:18 PM PST 23 |
113193200 ps |
T1229 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3290253671 |
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Dec 27 12:49:50 PM PST 23 |
Dec 27 01:02:38 PM PST 23 |
6288464800 ps |
T1230 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1127816778 |
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Dec 27 12:49:43 PM PST 23 |
Dec 27 12:49:59 PM PST 23 |
74398700 ps |
T1231 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.4154876375 |
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Dec 27 12:50:02 PM PST 23 |
Dec 27 12:50:25 PM PST 23 |
257955800 ps |
T1232 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4034355119 |
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Dec 27 12:49:42 PM PST 23 |
Dec 27 12:49:58 PM PST 23 |
42426100 ps |
T1233 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3170287566 |
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Dec 27 12:49:42 PM PST 23 |
Dec 27 12:49:57 PM PST 23 |
42164100 ps |
T1234 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3741400759 |
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Dec 27 12:49:47 PM PST 23 |
Dec 27 12:50:05 PM PST 23 |
50423000 ps |
T1235 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.3068896314 |
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Dec 27 12:50:41 PM PST 23 |
Dec 27 12:51:02 PM PST 23 |
27094900 ps |
T1236 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1425881297 |
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Dec 27 12:50:07 PM PST 23 |
Dec 27 12:50:29 PM PST 23 |
49561200 ps |
T1237 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2044481715 |
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Dec 27 12:49:50 PM PST 23 |
Dec 27 12:50:14 PM PST 23 |
180791500 ps |
T1238 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1123519233 |
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Dec 27 12:49:59 PM PST 23 |
Dec 27 12:50:19 PM PST 23 |
101219500 ps |
T1239 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.2962979274 |
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Dec 27 12:49:56 PM PST 23 |
Dec 27 12:50:28 PM PST 23 |
41547300 ps |
T1240 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1533092868 |
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Dec 27 12:50:05 PM PST 23 |
Dec 27 12:50:25 PM PST 23 |
20215800 ps |
T1241 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3992107187 |
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Dec 27 12:49:59 PM PST 23 |
Dec 27 12:50:18 PM PST 23 |
145317800 ps |
T1242 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.122389029 |
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Dec 27 12:49:50 PM PST 23 |
Dec 27 12:50:09 PM PST 23 |
50914800 ps |
T1243 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3303140095 |
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Dec 27 12:50:21 PM PST 23 |
Dec 27 12:50:45 PM PST 23 |
153864500 ps |
T1244 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.609853680 |
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Dec 27 12:50:08 PM PST 23 |
Dec 27 12:51:06 PM PST 23 |
1634055500 ps |
T1245 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.3457311137 |
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Dec 27 12:50:00 PM PST 23 |
Dec 27 12:50:18 PM PST 23 |
15235100 ps |
T1246 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2337542276 |
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Dec 27 12:49:26 PM PST 23 |
Dec 27 12:49:58 PM PST 23 |
64978600 ps |
T1247 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.341024421 |
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Dec 27 12:50:04 PM PST 23 |
Dec 27 12:50:24 PM PST 23 |
54028500 ps |
T1248 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.857544199 |
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Dec 27 12:49:55 PM PST 23 |
Dec 27 12:50:17 PM PST 23 |
69595300 ps |
T1249 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3171577714 |
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Dec 27 12:50:15 PM PST 23 |
Dec 27 12:50:38 PM PST 23 |
24501700 ps |
T1250 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.35311244 |
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Dec 27 12:50:15 PM PST 23 |
Dec 27 12:50:36 PM PST 23 |
111051500 ps |
T1251 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2158871348 |
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Dec 27 12:49:57 PM PST 23 |
Dec 27 12:50:15 PM PST 23 |
51718800 ps |
T249 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1877157604 |
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Dec 27 12:50:03 PM PST 23 |
Dec 27 12:50:23 PM PST 23 |
15302100 ps |