FLASH_CTRL Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.626m	47.222us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	25.930s	24.414us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.560s	68.188us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.320s	359.253us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.409m	12.854ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	51.620s	1.634ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.160s	69.595us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.320s	359.253us	20	20	100.00
		flash_ctrl_csr_aliasing	51.620s	1.634ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.560s	49.714us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.990s	16.274us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.770s	96.181us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.086m	219.306us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	29.300m	108.563ms	3	3	100.00
		flash_ctrl_hw_rma_reset	14.949m	160.195ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.820s	25.259us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	40.726m	556.093ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.153m	13.408ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	20.180s	415.403us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	58.036m	212.281ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.721m	4.012ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	39.690s	485.165us	40	40	100.00
		flash_ctrl_rw_evict_all_en	39.740s	312.102us	39	40	97.50
		flash_ctrl_re_evict	41.080s	147.190us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.622m	6.585ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.622m	6.585ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.779m	93.626ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.070s	1.111ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	15.983m	2.931ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	39.677m	120.751ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.280m	950.472us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	43.693m	1.603ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.800s	24.742us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.169m	12.394ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.600s	19.509us	48	50	96.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.470s	17.067us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	33.120m	951.947us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.118m	3.004ms	50	50	100.00
		flash_ctrl_otp_reset	2.261m	150.703us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	29.300m	108.563ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.048m	1.047ms	40	40	100.00
		flash_ctrl_intr_wr	2.103m	19.519ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.378m	78.939ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.060m	234.481ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.627m	12.162ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.216m	8.280ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.660s	31.656us	5	5	100.00
		flash_ctrl_ro_derr	2.456m	2.261ms	10	10	100.00
		flash_ctrl_rw_derr	11.782m	14.660ms	10	10	100.00
		flash_ctrl_derr_detect	1.751m	293.658us	5	5	100.00
		flash_ctrl_integrity	13.623m	28.334ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.220s	24.557us	5	5	100.00
		flash_ctrl_ro_serr	2.568m	2.956ms	10	10	100.00
		flash_ctrl_rw_serr	11.310m	4.481ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.320m	2.700ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.331m	13.253ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.370m	10.826ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.310s	67.161us	1	1	100.00
		flash_ctrl_read_word_sweep	14.120s	26.244us	1	1	100.00
		flash_ctrl_ro	1.941m	1.100ms	20	20	100.00
		flash_ctrl_rw	9.544m	22.491ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	38.420s	4.122ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	14.582m	41.329ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.552m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	15.710s	350.648us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.120s	68.777us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.280s	212.596us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.280s	212.596us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.560s	68.188us	5	5	100.00
		flash_ctrl_csr_rw	17.320s	359.253us	20	20	100.00
		flash_ctrl_csr_aliasing	51.620s	1.634ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.570s	127.895us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.560s	68.188us	5	5	100.00
		flash_ctrl_csr_rw	17.320s	359.253us	20	20	100.00
		flash_ctrl_csr_aliasing	51.620s	1.634ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.570s	127.895us	20	20	100.00
V2		TOTAL			1009	1013	99.61
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.800s	49.907us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.800s	49.907us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.800s	49.907us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.800s	49.907us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.770s	14.802us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.309h	2.002ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.082m	2.048ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.082m	2.048ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.082m	2.048ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.690s	613.825us	3	3	100.00
		flash_ctrl_wr_intg	14.630s	59.117us	2	3	66.67
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.626m	47.222us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.261m	150.703us	80	80	100.00
		flash_ctrl_disable	22.600s	19.509us	48	50	96.00
		flash_ctrl_sec_info_access	1.539m	6.960ms	50	50	100.00
		flash_ctrl_connect	16.470s	17.067us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.140s	37.134us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.320s	359.253us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.800s	49.907us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.320s	359.253us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.800s	49.907us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.320s	359.253us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.800s	49.907us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.600s	19.509us	48	50	96.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.690s	613.825us	3	3	100.00
		flash_ctrl_access_after_disable	13.740s	39.263us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.600s	19.509us	48	50	96.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.070s	1.111ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.544m	22.491ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.310m	4.481ms	10	10	100.00
		flash_ctrl_rw_derr	11.782m	14.660ms	10	10	100.00
		flash_ctrl_integrity	13.623m	28.334ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	29.300m	108.563ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.309h	2.002ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.309h	2.002ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.309h	2.002ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.309h	2.002ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	17.470s	123.718us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.380s	47.973us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.110s	48.623us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.309h	2.002ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.309h	2.002ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.309h	2.002ms	5	5	100.00
V2S		TOTAL			143	144	99.31
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.330s	202.219us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1278	99.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	52	94.55
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.67	95.88	94.21	98.95	92.52	98.51	98.30	98.36

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

0.flash_ctrl_rw_evict_all_en.94302959580984929142384978091161468587658561908311339843123222006729211573538
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest/run.log

  [make]: simulate
  cd /workspace/0.flash_ctrl_rw_evict_all_en/latest && /workspace/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961738018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict_all_en.961738018
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Dec 27 13:33 2023
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 2.flash_ctrl_full_mem_access.52640959820117526555991849754775764574184358556299573020479768730209091456474
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:3627982e-4f05-4587-b238-fc077de79a32
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank1] *: obs:exp *f_f_10a1239f_7ea14808:4d_f_a500b512_d98cac5e mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 2.flash_ctrl_wr_intg.56909715292503614827938687704121971032236909630705081776889363841750000392510
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 23988.9 ns: (flash_ctrl_otf_scoreboard.sv:367) [wdata_page0_comp_bank1]    0: obs:exp    7f_f_10a1239f_7ea14808:4d_f_a500b512_d98cac5e  mismatch!!
  UVM_INFO @ 23988.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79561) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

16.flash_ctrl_disable.90119185383335440200866577681218461785882231295845222295199238260280566309723
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 9779.7 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79561) { a_addr: 'hb4a04  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb8  a_opcode: 'h4  a_user: 'h2482a  d_param: 'h0  d_source: 'hb8  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 9779.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@84365) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

28.flash_ctrl_disable.35345685107374764621822812147993676975548809218225789271910360242356741167550
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 9230.4 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@84365) { a_addr: 'hd24cc  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h59  a_opcode: 'h4  a_user: 'h270aa  d_param: 'h0  d_source: 'h59  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 9230.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---