Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	314380	1		T45	1		T52	5		T53	5
all_values[1]	314380	1		T45	1		T52	5		T53	5
all_values[2]	314380	1		T45	1		T52	5		T53	5
all_values[3]	314380	1		T45	1		T52	5		T53	5
all_values[4]	314380	1		T45	1		T52	5		T53	5
all_values[5]	314380	1		T45	1		T52	5		T53	5

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	9954	1		T45	6		T52	11		T53	16
auto[1]	1876326	1		T52	19		T53	14		T54	21

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1532246	1		T45	6		T52	19		T53	17
auto[1]	354034	1		T52	11		T53	13		T54	13

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1228	1		T45	1		T53	1		T125	2
all_values[0]	auto[0]	auto[1]	420	1		T52	1		T53	2		T184	1
all_values[0]	auto[1]	auto[0]	248888	1		T52	4		T53	2		T54	4
all_values[0]	auto[1]	auto[1]	63844	1		T54	1		T125	2		T311	2
all_values[1]	auto[0]	auto[0]	1608	1		T45	1		T52	4		T54	1
all_values[1]	auto[0]	auto[1]	56	1		T246	1		T248	3		T312	2
all_values[1]	auto[1]	auto[0]	258218	1		T53	3		T54	2		T125	3
all_values[1]	auto[1]	auto[1]	54498	1		T52	1		T53	2		T54	2
all_values[2]	auto[0]	auto[0]	1545	1		T45	1		T52	1		T53	4
all_values[2]	auto[0]	auto[1]	122	1		T54	1		T125	1		T311	1
all_values[2]	auto[1]	auto[0]	306820	1		T52	2		T53	1		T54	1
all_values[2]	auto[1]	auto[1]	5893	1		T52	2		T54	2		T125	2
all_values[3]	auto[0]	auto[0]	1527	1		T45	1		T53	2		T54	4
all_values[3]	auto[0]	auto[1]	135	1		T52	1		T53	3		T184	2
all_values[3]	auto[1]	auto[0]	180466	1		T52	2		T125	3		T246	3
all_values[3]	auto[1]	auto[1]	132252	1		T52	2		T54	1		T184	2
all_values[4]	auto[0]	auto[0]	1138	1		T45	1		T53	1		T184	1
all_values[4]	auto[0]	auto[1]	513	1		T52	1		T53	2		T54	1
all_values[4]	auto[1]	auto[0]	216636	1		T52	1		T53	2		T54	1
all_values[4]	auto[1]	auto[1]	96093	1		T52	3		T54	3		T184	3
all_values[5]	auto[0]	auto[0]	1520	1		T45	1		T52	3		T54	1
all_values[5]	auto[0]	auto[1]	142	1		T53	1		T311	2		T247	2
all_values[5]	auto[1]	auto[0]	312652	1		T52	2		T53	1		T54	2
all_values[5]	auto[1]	auto[1]	66	1		T53	3		T54	2		T246	4