Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T100 |
1 |
|
T82 |
12 |
|
T337 |
1 |
| others[1] |
201 |
1 |
|
T82 |
3 |
|
T88 |
10 |
|
T115 |
1 |
| others[2] |
208 |
1 |
|
T82 |
8 |
|
T73 |
1 |
|
T338 |
1 |
| others[3] |
364 |
1 |
|
T82 |
19 |
|
T27 |
1 |
|
T73 |
1 |
| false |
110 |
1 |
|
T26 |
1 |
|
T82 |
6 |
|
T88 |
2 |
| true |
12436 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7940 |
1 |
|
T311 |
1 |
|
T122 |
1 |
|
T124 |
1 |
| others[1] |
1251 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T247 |
1 |
| others[2] |
1261 |
1 |
|
T53 |
1 |
|
T118 |
1 |
|
T248 |
1 |
| others[3] |
2041 |
1 |
|
T54 |
1 |
|
T184 |
1 |
|
T116 |
1 |
| false |
632 |
1 |
|
T45 |
1 |
|
T117 |
1 |
|
T252 |
1 |
| true |
423 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7983 |
1 |
|
T125 |
1 |
|
T118 |
1 |
|
T120 |
1 |
| others[1] |
1253 |
1 |
|
T54 |
1 |
|
T247 |
1 |
|
T248 |
1 |
| others[2] |
1201 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T117 |
1 |
| others[3] |
2013 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T311 |
1 |
| false |
676 |
1 |
|
T116 |
1 |
|
T252 |
1 |
|
T347 |
1 |
| true |
422 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T99 |
1 |
|
T82 |
5 |
|
T88 |
4 |
| others[1] |
100 |
1 |
|
T82 |
6 |
|
T73 |
1 |
|
T338 |
1 |
| others[2] |
108 |
1 |
|
T20 |
1 |
|
T82 |
4 |
|
T64 |
1 |
| others[3] |
179 |
1 |
|
T82 |
5 |
|
T235 |
1 |
|
T339 |
1 |
| false |
51 |
1 |
|
T82 |
2 |
|
T73 |
1 |
|
T338 |
1 |
| true |
13004 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
264 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T82 |
6 |
| others[1] |
219 |
1 |
|
T82 |
7 |
|
T73 |
2 |
|
T235 |
1 |
| others[2] |
242 |
1 |
|
T82 |
21 |
|
T341 |
1 |
|
T344 |
1 |
| others[3] |
395 |
1 |
|
T4 |
1 |
|
T82 |
14 |
|
T88 |
19 |
| false |
129 |
1 |
|
T99 |
1 |
|
T82 |
7 |
|
T57 |
1 |
| true |
12299 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7779 |
1 |
|
T45 |
1 |
|
T120 |
1 |
|
T247 |
1 |
| others[1] |
1039 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T311 |
1 |
| others[2] |
1077 |
1 |
|
T184 |
1 |
|
T124 |
1 |
|
T128 |
1 |
| others[3] |
1731 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T117 |
1 |
| false |
543 |
1 |
|
T116 |
1 |
|
T122 |
1 |
|
T252 |
1 |
| true |
1379 |
1 |
|
T6 |
40 |
|
T22 |
1 |
|
T30 |
33 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T82 |
10 |
|
T341 |
1 |
|
T348 |
1 |
| others[1] |
215 |
1 |
|
T82 |
15 |
|
T269 |
1 |
|
T337 |
1 |
| others[2] |
197 |
1 |
|
T4 |
1 |
|
T82 |
7 |
|
T88 |
7 |
| others[3] |
387 |
1 |
|
T22 |
1 |
|
T82 |
13 |
|
T338 |
2 |
| false |
111 |
1 |
|
T100 |
1 |
|
T82 |
3 |
|
T346 |
1 |
| true |
12386 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T23 |
1 |
|
T158 |
1 |
|
T82 |
10 |
| others[1] |
198 |
1 |
|
T26 |
1 |
|
T82 |
10 |
|
T39 |
1 |
| others[2] |
193 |
1 |
|
T100 |
1 |
|
T82 |
4 |
|
T88 |
7 |
| others[3] |
392 |
1 |
|
T99 |
1 |
|
T82 |
13 |
|
T337 |
1 |
| false |
131 |
1 |
|
T82 |
6 |
|
T339 |
1 |
|
T346 |
1 |
| true |
12407 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7915 |
1 |
|
T120 |
1 |
|
T246 |
1 |
|
T122 |
1 |
| others[1] |
1223 |
1 |
|
T118 |
1 |
|
T124 |
1 |
|
T126 |
1 |
| others[2] |
1226 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T54 |
1 |
| others[3] |
2089 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T116 |
1 |
| false |
666 |
1 |
|
T300 |
1 |
|
T313 |
1 |
|
T2 |
1 |
| true |
429 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1215 |
1 |
|
T52 |
1 |
|
T116 |
1 |
|
T118 |
1 |
| others[1] |
1216 |
1 |
|
T53 |
1 |
|
T184 |
1 |
|
T311 |
1 |
| others[2] |
1247 |
1 |
|
T54 |
1 |
|
T300 |
1 |
|
T127 |
1 |
| others[3] |
2047 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T246 |
1 |
| false |
654 |
1 |
|
T124 |
1 |
|
T6 |
10 |
|
T30 |
8 |
| true |
428 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T99 |
1 |
|
T82 |
6 |
|
T64 |
1 |
| others[1] |
100 |
1 |
|
T82 |
8 |
|
T73 |
1 |
|
T88 |
3 |
| others[2] |
99 |
1 |
|
T20 |
1 |
|
T158 |
1 |
|
T82 |
2 |
| others[3] |
191 |
1 |
|
T82 |
6 |
|
T338 |
1 |
|
T337 |
1 |
| false |
55 |
1 |
|
T82 |
2 |
|
T88 |
3 |
|
T89 |
1 |
| true |
6257 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T23 |
1 |
|
T82 |
9 |
|
T39 |
1 |
| others[1] |
240 |
1 |
|
T100 |
1 |
|
T82 |
15 |
|
T214 |
1 |
| others[2] |
235 |
1 |
|
T34 |
1 |
|
T82 |
13 |
|
T73 |
1 |
| others[3] |
367 |
1 |
|
T26 |
1 |
|
T82 |
11 |
|
T27 |
1 |
| false |
117 |
1 |
|
T82 |
2 |
|
T73 |
1 |
|
T88 |
3 |
| true |
5621 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1078 |
1 |
|
T184 |
1 |
|
T118 |
1 |
|
T252 |
1 |
| others[1] |
986 |
1 |
|
T311 |
1 |
|
T120 |
1 |
|
T246 |
1 |
| others[2] |
1029 |
1 |
|
T53 |
1 |
|
T117 |
1 |
|
T247 |
1 |
| others[3] |
1732 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T54 |
1 |
| false |
572 |
1 |
|
T12 |
1 |
|
T6 |
5 |
|
T30 |
4 |
| true |
1410 |
1 |
|
T4 |
1 |
|
T6 |
52 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T23 |
1 |
|
T82 |
6 |
|
T73 |
1 |
| others[1] |
223 |
1 |
|
T26 |
1 |
|
T99 |
1 |
|
T158 |
1 |
| others[2] |
230 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T82 |
8 |
| others[3] |
390 |
1 |
|
T82 |
19 |
|
T28 |
1 |
|
T269 |
1 |
| false |
116 |
1 |
|
T100 |
1 |
|
T82 |
6 |
|
T344 |
1 |
| true |
5599 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T82 |
8 |
|
T27 |
1 |
|
T235 |
1 |
| others[1] |
247 |
1 |
|
T26 |
1 |
|
T82 |
8 |
|
T88 |
14 |
| others[2] |
213 |
1 |
|
T23 |
1 |
|
T82 |
10 |
|
T73 |
1 |
| others[3] |
365 |
1 |
|
T99 |
1 |
|
T100 |
1 |
|
T82 |
14 |
| false |
118 |
1 |
|
T82 |
2 |
|
T88 |
4 |
|
T89 |
8 |
| true |
5660 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T54 |
1 |
|
T247 |
1 |
|
T312 |
1 |
| others[1] |
1241 |
1 |
|
T45 |
1 |
|
T116 |
1 |
|
T311 |
1 |
| others[2] |
1251 |
1 |
|
T53 |
1 |
|
T184 |
1 |
|
T127 |
1 |
| others[3] |
1989 |
1 |
|
T125 |
1 |
|
T118 |
1 |
|
T120 |
1 |
| false |
647 |
1 |
|
T52 |
1 |
|
T252 |
1 |
|
T300 |
1 |
| true |
431 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T117 |
1 |
|
T118 |
1 |
|
T300 |
1 |
| others[1] |
1240 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T184 |
1 |
| others[2] |
1198 |
1 |
|
T246 |
1 |
|
T248 |
1 |
|
T252 |
1 |
| others[3] |
2096 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T116 |
1 |
| false |
600 |
1 |
|
T53 |
1 |
|
T6 |
7 |
|
T21 |
1 |
| true |
426 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T26 |
1 |
|
T82 |
4 |
|
T339 |
1 |
| others[1] |
102 |
1 |
|
T99 |
1 |
|
T73 |
1 |
|
T88 |
5 |
| others[2] |
91 |
1 |
|
T82 |
5 |
|
T337 |
2 |
|
T88 |
5 |
| others[3] |
177 |
1 |
|
T20 |
1 |
|
T158 |
1 |
|
T82 |
8 |
| false |
51 |
1 |
|
T82 |
1 |
|
T73 |
1 |
|
T235 |
1 |
| true |
6285 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T99 |
1 |
|
T82 |
10 |
|
T73 |
2 |
| others[1] |
236 |
1 |
|
T100 |
1 |
|
T82 |
9 |
|
T64 |
1 |
| others[2] |
226 |
1 |
|
T82 |
11 |
|
T344 |
1 |
|
T345 |
1 |
| others[3] |
392 |
1 |
|
T22 |
1 |
|
T82 |
20 |
|
T61 |
1 |
| false |
127 |
1 |
|
T82 |
2 |
|
T271 |
1 |
|
T88 |
9 |
| true |
5579 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1013 |
1 |
|
T54 |
1 |
|
T117 |
1 |
|
T122 |
1 |
| others[1] |
1078 |
1 |
|
T125 |
1 |
|
T120 |
1 |
|
T312 |
1 |
| others[2] |
1038 |
1 |
|
T45 |
1 |
|
T248 |
1 |
|
T126 |
1 |
| others[3] |
1735 |
1 |
|
T53 |
1 |
|
T116 |
1 |
|
T311 |
1 |
| false |
556 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T247 |
1 |
| true |
1387 |
1 |
|
T6 |
44 |
|
T30 |
28 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T23 |
1 |
| others[1] |
225 |
1 |
|
T82 |
10 |
|
T348 |
1 |
|
T88 |
14 |
| others[2] |
266 |
1 |
|
T99 |
1 |
|
T82 |
6 |
|
T28 |
1 |
| others[3] |
342 |
1 |
|
T82 |
22 |
|
T27 |
1 |
|
T269 |
1 |
| false |
123 |
1 |
|
T82 |
1 |
|
T346 |
1 |
|
T88 |
8 |
| true |
5616 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T99 |
1 |
|
T82 |
5 |
|
T39 |
1 |
| others[1] |
230 |
1 |
|
T20 |
1 |
|
T158 |
1 |
|
T82 |
11 |
| others[2] |
209 |
1 |
|
T100 |
1 |
|
T82 |
10 |
|
T204 |
1 |
| others[3] |
383 |
1 |
|
T23 |
1 |
|
T82 |
19 |
|
T339 |
1 |
| false |
110 |
1 |
|
T82 |
4 |
|
T88 |
4 |
|
T89 |
7 |
| true |
5664 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1238 |
1 |
|
T125 |
1 |
|
T184 |
1 |
|
T313 |
1 |
| others[1] |
1229 |
1 |
|
T128 |
1 |
|
T350 |
1 |
|
T1 |
1 |
| others[2] |
1224 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T116 |
1 |
| others[3] |
2042 |
1 |
|
T52 |
1 |
|
T311 |
1 |
|
T117 |
1 |
| false |
628 |
1 |
|
T45 |
1 |
|
T126 |
1 |
|
T6 |
12 |
| true |
446 |
1 |
|
T22 |
1 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T117 |
1 |
|
T124 |
1 |
|
T300 |
1 |
| others[1] |
1212 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T184 |
1 |
| others[2] |
1267 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T120 |
1 |
| others[3] |
2073 |
1 |
|
T118 |
1 |
|
T122 |
1 |
|
T247 |
1 |
| false |
606 |
1 |
|
T45 |
1 |
|
T116 |
1 |
|
T126 |
1 |
| true |
420 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
95 |
1 |
|
T82 |
3 |
|
T204 |
1 |
|
T338 |
1 |
| others[1] |
110 |
1 |
|
T99 |
1 |
|
T82 |
6 |
|
T28 |
1 |
| others[2] |
97 |
1 |
|
T82 |
2 |
|
T73 |
1 |
|
T235 |
1 |
| others[3] |
175 |
1 |
|
T20 |
1 |
|
T82 |
8 |
|
T73 |
1 |
| false |
72 |
1 |
|
T82 |
6 |
|
T339 |
1 |
|
T337 |
1 |
| true |
6258 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T82 |
11 |
|
T73 |
2 |
|
T205 |
1 |
| others[1] |
237 |
1 |
|
T82 |
11 |
|
T348 |
1 |
|
T346 |
1 |
| others[2] |
240 |
1 |
|
T82 |
12 |
|
T64 |
1 |
|
T235 |
1 |
| others[3] |
402 |
1 |
|
T34 |
1 |
|
T82 |
11 |
|
T57 |
1 |
| false |
138 |
1 |
|
T82 |
5 |
|
T338 |
1 |
|
T88 |
9 |
| true |
5536 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1077 |
1 |
|
T314 |
1 |
|
T6 |
11 |
|
T22 |
1 |
| others[1] |
1098 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T246 |
1 |
| others[2] |
1033 |
1 |
|
T247 |
1 |
|
T124 |
1 |
|
T312 |
1 |
| others[3] |
1680 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| false |
553 |
1 |
|
T116 |
1 |
|
T311 |
1 |
|
T120 |
1 |
| true |
1366 |
1 |
|
T6 |
52 |
|
T26 |
1 |
|
T30 |
26 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T82 |
8 |
|
T341 |
1 |
|
T338 |
1 |
| others[1] |
216 |
1 |
|
T82 |
7 |
|
T204 |
1 |
|
T348 |
1 |
| others[2] |
242 |
1 |
|
T23 |
1 |
|
T158 |
1 |
|
T82 |
10 |
| others[3] |
369 |
1 |
|
T22 |
1 |
|
T82 |
17 |
|
T27 |
1 |
| false |
114 |
1 |
|
T20 |
1 |
|
T26 |
1 |
|
T99 |
1 |
| true |
5640 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T82 |
6 |
| others[1] |
218 |
1 |
|
T99 |
1 |
|
T82 |
13 |
|
T235 |
1 |
| others[2] |
231 |
1 |
|
T82 |
10 |
|
T64 |
1 |
|
T28 |
1 |
| others[3] |
374 |
1 |
|
T158 |
1 |
|
T82 |
22 |
|
T39 |
1 |
| false |
118 |
1 |
|
T82 |
5 |
|
T88 |
2 |
|
T115 |
1 |
| true |
5642 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T125 |
1 |
|
T252 |
1 |
|
T300 |
1 |
| others[1] |
1269 |
1 |
|
T45 |
1 |
|
T117 |
1 |
|
T120 |
1 |
| others[2] |
1178 |
1 |
|
T54 |
1 |
|
T116 |
1 |
|
T118 |
1 |
| others[3] |
2040 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T311 |
1 |
| false |
653 |
1 |
|
T184 |
1 |
|
T122 |
1 |
|
T248 |
1 |
| true |
437 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T184 |
1 |
|
T117 |
1 |
|
T122 |
1 |
| others[1] |
1248 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
| others[2] |
1314 |
1 |
|
T54 |
1 |
|
T125 |
1 |
|
T311 |
1 |
| others[3] |
1956 |
1 |
|
T120 |
1 |
|
T246 |
1 |
|
T126 |
1 |
| false |
645 |
1 |
|
T6 |
12 |
|
T7 |
1 |
|
T30 |
8 |
| true |
415 |
1 |
|
T22 |
1 |
|
T34 |
1 |
|
T26 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |