Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T82 |
2 |
|
T73 |
1 |
|
T341 |
1 |
| others[1] |
100 |
1 |
|
T20 |
1 |
|
T82 |
7 |
|
T88 |
5 |
| others[2] |
108 |
1 |
|
T82 |
8 |
|
T64 |
1 |
|
T235 |
1 |
| others[3] |
181 |
1 |
|
T99 |
1 |
|
T82 |
8 |
|
T28 |
1 |
| false |
51 |
1 |
|
T82 |
3 |
|
T73 |
1 |
|
T88 |
2 |
| true |
6274 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T82 |
7 |
|
T28 |
1 |
|
T341 |
1 |
| others[1] |
222 |
1 |
|
T158 |
1 |
|
T82 |
9 |
|
T57 |
1 |
| others[2] |
254 |
1 |
|
T82 |
9 |
|
T203 |
1 |
|
T271 |
1 |
| others[3] |
370 |
1 |
|
T82 |
18 |
|
T337 |
1 |
|
T346 |
1 |
| false |
143 |
1 |
|
T82 |
5 |
|
T73 |
1 |
|
T338 |
1 |
| true |
5591 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1095 |
1 |
|
T125 |
1 |
|
T252 |
1 |
|
T350 |
1 |
| others[1] |
1016 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T120 |
1 |
| others[2] |
1088 |
1 |
|
T52 |
1 |
|
T116 |
1 |
|
T311 |
1 |
| others[3] |
1686 |
1 |
|
T54 |
1 |
|
T184 |
1 |
|
T246 |
1 |
| false |
532 |
1 |
|
T117 |
1 |
|
T6 |
3 |
|
T30 |
1 |
| true |
1390 |
1 |
|
T4 |
1 |
|
T6 |
46 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T82 |
10 |
|
T73 |
1 |
|
T88 |
7 |
| others[1] |
222 |
1 |
|
T82 |
12 |
|
T28 |
1 |
|
T344 |
1 |
| others[2] |
231 |
1 |
|
T158 |
1 |
|
T82 |
12 |
|
T88 |
10 |
| others[3] |
376 |
1 |
|
T20 |
1 |
|
T22 |
1 |
|
T23 |
1 |
| false |
123 |
1 |
|
T82 |
6 |
|
T348 |
1 |
|
T88 |
4 |
| true |
5628 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T82 |
17 |
|
T337 |
1 |
|
T88 |
12 |
| others[1] |
212 |
1 |
|
T99 |
1 |
|
T82 |
9 |
|
T88 |
6 |
| others[2] |
222 |
1 |
|
T82 |
11 |
|
T39 |
1 |
|
T338 |
1 |
| others[3] |
378 |
1 |
|
T100 |
1 |
|
T82 |
9 |
|
T64 |
1 |
| false |
123 |
1 |
|
T82 |
5 |
|
T345 |
1 |
|
T88 |
7 |
| true |
5661 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T311 |
1 |
|
T122 |
1 |
|
T247 |
1 |
| others[1] |
1234 |
1 |
|
T184 |
1 |
|
T116 |
1 |
|
T6 |
13 |
| others[2] |
1220 |
1 |
|
T53 |
1 |
|
T124 |
1 |
|
T312 |
1 |
| others[3] |
2030 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| false |
616 |
1 |
|
T45 |
1 |
|
T120 |
1 |
|
T300 |
1 |
| true |
434 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T52 |
1 |
|
T118 |
1 |
|
T246 |
1 |
| others[1] |
1176 |
1 |
|
T116 |
1 |
|
T311 |
1 |
|
T117 |
1 |
| others[2] |
1214 |
1 |
|
T120 |
1 |
|
T248 |
1 |
|
T124 |
1 |
| others[3] |
2129 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| false |
642 |
1 |
|
T53 |
1 |
|
T343 |
1 |
|
T313 |
1 |
| true |
418 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T82 |
4 |
|
T73 |
1 |
|
T338 |
1 |
| others[1] |
94 |
1 |
|
T82 |
4 |
|
T27 |
1 |
|
T73 |
1 |
| others[2] |
117 |
1 |
|
T82 |
6 |
|
T338 |
1 |
|
T88 |
4 |
| others[3] |
161 |
1 |
|
T20 |
1 |
|
T82 |
4 |
|
T337 |
1 |
| false |
58 |
1 |
|
T23 |
1 |
|
T99 |
1 |
|
T82 |
4 |
| true |
6272 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T4 |
1 |
|
T99 |
1 |
|
T82 |
10 |
| others[1] |
213 |
1 |
|
T82 |
12 |
|
T27 |
1 |
|
T337 |
1 |
| others[2] |
236 |
1 |
|
T82 |
12 |
|
T203 |
1 |
|
T73 |
1 |
| others[3] |
402 |
1 |
|
T20 |
1 |
|
T82 |
14 |
|
T339 |
1 |
| false |
123 |
1 |
|
T82 |
6 |
|
T348 |
1 |
|
T88 |
2 |
| true |
5595 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1014 |
1 |
|
T246 |
1 |
|
T312 |
1 |
|
T126 |
1 |
| others[1] |
1036 |
1 |
|
T311 |
1 |
|
T122 |
1 |
|
T248 |
1 |
| others[2] |
992 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T118 |
1 |
| others[3] |
1818 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T125 |
1 |
| false |
538 |
1 |
|
T347 |
1 |
|
T6 |
7 |
|
T30 |
7 |
| true |
1409 |
1 |
|
T4 |
1 |
|
T6 |
53 |
|
T30 |
18 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T82 |
10 |
|
T27 |
1 |
|
T337 |
1 |
| others[1] |
227 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T82 |
7 |
| others[2] |
222 |
1 |
|
T82 |
9 |
|
T204 |
1 |
|
T346 |
1 |
| others[3] |
382 |
1 |
|
T158 |
1 |
|
T100 |
1 |
|
T82 |
16 |
| false |
124 |
1 |
|
T82 |
6 |
|
T88 |
3 |
|
T101 |
1 |
| true |
5645 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T26 |
1 |
|
T82 |
10 |
|
T88 |
12 |
| others[1] |
206 |
1 |
|
T82 |
12 |
|
T341 |
1 |
|
T338 |
1 |
| others[2] |
202 |
1 |
|
T158 |
1 |
|
T82 |
12 |
|
T39 |
1 |
| others[3] |
373 |
1 |
|
T20 |
1 |
|
T100 |
1 |
|
T82 |
15 |
| false |
109 |
1 |
|
T82 |
4 |
|
T73 |
1 |
|
T58 |
1 |
| true |
5708 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1218 |
1 |
|
T54 |
1 |
|
T116 |
1 |
|
T120 |
1 |
| others[1] |
1170 |
1 |
|
T52 |
1 |
|
T118 |
1 |
|
T246 |
1 |
| others[2] |
1277 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T247 |
1 |
| others[3] |
2096 |
1 |
|
T184 |
1 |
|
T122 |
1 |
|
T343 |
1 |
| false |
594 |
1 |
|
T125 |
1 |
|
T311 |
1 |
|
T117 |
1 |
| true |
452 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1216 |
1 |
|
T45 |
1 |
|
T122 |
1 |
|
T247 |
1 |
| others[1] |
1206 |
1 |
|
T53 |
1 |
|
T116 |
1 |
|
T118 |
1 |
| others[2] |
1338 |
1 |
|
T117 |
1 |
|
T312 |
1 |
|
T2 |
1 |
| others[3] |
2006 |
1 |
|
T54 |
1 |
|
T125 |
1 |
|
T311 |
1 |
| false |
629 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T6 |
10 |
| true |
412 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T82 |
6 |
|
T337 |
1 |
|
T88 |
4 |
| others[1] |
105 |
1 |
|
T82 |
5 |
|
T88 |
5 |
|
T340 |
2 |
| others[2] |
109 |
1 |
|
T82 |
4 |
|
T339 |
1 |
|
T88 |
4 |
| others[3] |
183 |
1 |
|
T20 |
1 |
|
T26 |
1 |
|
T99 |
1 |
| false |
44 |
1 |
|
T73 |
1 |
|
T338 |
1 |
|
T88 |
2 |
| true |
6257 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T82 |
5 |
|
T64 |
1 |
|
T235 |
1 |
| others[1] |
249 |
1 |
|
T82 |
12 |
|
T203 |
1 |
|
T339 |
1 |
| others[2] |
229 |
1 |
|
T26 |
1 |
|
T23 |
1 |
|
T82 |
12 |
| others[3] |
403 |
1 |
|
T22 |
1 |
|
T82 |
10 |
|
T73 |
1 |
| false |
148 |
1 |
|
T82 |
6 |
|
T73 |
1 |
|
T341 |
1 |
| true |
5552 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1019 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T184 |
1 |
| others[1] |
1058 |
1 |
|
T52 |
1 |
|
T246 |
1 |
|
T122 |
1 |
| others[2] |
1022 |
1 |
|
T125 |
1 |
|
T116 |
1 |
|
T343 |
1 |
| others[3] |
1764 |
1 |
|
T54 |
1 |
|
T311 |
1 |
|
T120 |
1 |
| false |
529 |
1 |
|
T6 |
4 |
|
T30 |
4 |
|
T100 |
1 |
| true |
1415 |
1 |
|
T4 |
1 |
|
T6 |
54 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T22 |
1 |
|
T82 |
8 |
|
T214 |
1 |
| others[1] |
248 |
1 |
|
T82 |
11 |
|
T73 |
1 |
|
T337 |
1 |
| others[2] |
225 |
1 |
|
T20 |
1 |
|
T158 |
1 |
|
T82 |
11 |
| others[3] |
425 |
1 |
|
T4 |
1 |
|
T99 |
1 |
|
T82 |
13 |
| false |
102 |
1 |
|
T82 |
8 |
|
T88 |
2 |
|
T89 |
4 |
| true |
5577 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T82 |
7 |
|
T27 |
1 |
|
T73 |
1 |
| others[1] |
242 |
1 |
|
T20 |
1 |
|
T158 |
1 |
|
T82 |
11 |
| others[2] |
233 |
1 |
|
T99 |
1 |
|
T82 |
9 |
|
T28 |
1 |
| others[3] |
353 |
1 |
|
T100 |
1 |
|
T82 |
16 |
|
T88 |
17 |
| false |
116 |
1 |
|
T82 |
5 |
|
T88 |
5 |
|
T89 |
2 |
| true |
5643 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T54 |
1 |
|
T116 |
1 |
|
T246 |
1 |
| others[1] |
1187 |
1 |
|
T6 |
14 |
|
T25 |
1 |
|
T30 |
14 |
| others[2] |
1267 |
1 |
|
T45 |
1 |
|
T118 |
1 |
|
T120 |
1 |
| others[3] |
2057 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T125 |
1 |
| false |
645 |
1 |
|
T127 |
1 |
|
T313 |
1 |
|
T314 |
1 |
| true |
447 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T247 |
1 |
|
T127 |
1 |
|
T347 |
1 |
| others[1] |
1253 |
1 |
|
T54 |
1 |
|
T184 |
1 |
|
T117 |
1 |
| others[2] |
1225 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T116 |
1 |
| others[3] |
2048 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T311 |
1 |
| false |
611 |
1 |
|
T120 |
1 |
|
T6 |
11 |
|
T30 |
7 |
| true |
419 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T82 |
3 |
|
T338 |
1 |
|
T88 |
4 |
| others[1] |
104 |
1 |
|
T20 |
1 |
|
T82 |
7 |
|
T338 |
1 |
| others[2] |
109 |
1 |
|
T82 |
2 |
|
T88 |
3 |
|
T115 |
1 |
| others[3] |
168 |
1 |
|
T82 |
5 |
|
T73 |
1 |
|
T235 |
1 |
| false |
52 |
1 |
|
T99 |
1 |
|
T82 |
3 |
|
T73 |
1 |
| true |
6266 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T99 |
1 |
|
T82 |
14 |
|
T57 |
1 |
| others[1] |
221 |
1 |
|
T82 |
6 |
|
T337 |
1 |
|
T107 |
1 |
| others[2] |
238 |
1 |
|
T34 |
1 |
|
T82 |
7 |
|
T205 |
1 |
| others[3] |
396 |
1 |
|
T20 |
1 |
|
T22 |
1 |
|
T26 |
1 |
| false |
144 |
1 |
|
T82 |
5 |
|
T28 |
1 |
|
T204 |
1 |
| true |
5582 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1063 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T118 |
1 |
| others[1] |
1086 |
1 |
|
T45 |
1 |
|
T248 |
1 |
|
T252 |
1 |
| others[2] |
1021 |
1 |
|
T311 |
1 |
|
T117 |
1 |
|
T124 |
1 |
| others[3] |
1711 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T184 |
1 |
| false |
486 |
1 |
|
T120 |
1 |
|
T246 |
1 |
|
T122 |
1 |
| true |
1440 |
1 |
|
T6 |
52 |
|
T22 |
1 |
|
T30 |
25 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T158 |
1 |
|
T82 |
6 |
|
T39 |
1 |
| others[1] |
239 |
1 |
|
T22 |
1 |
|
T82 |
15 |
|
T269 |
1 |
| others[2] |
240 |
1 |
|
T82 |
10 |
|
T27 |
1 |
|
T339 |
1 |
| others[3] |
385 |
1 |
|
T4 |
1 |
|
T26 |
1 |
|
T82 |
18 |
| false |
108 |
1 |
|
T82 |
4 |
|
T58 |
1 |
|
T88 |
1 |
| true |
5593 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T82 |
8 |
|
T39 |
1 |
|
T337 |
1 |
| others[1] |
213 |
1 |
|
T100 |
1 |
|
T82 |
12 |
|
T235 |
1 |
| others[2] |
253 |
1 |
|
T82 |
13 |
|
T338 |
1 |
|
T88 |
9 |
| others[3] |
393 |
1 |
|
T23 |
1 |
|
T158 |
1 |
|
T82 |
20 |
| false |
114 |
1 |
|
T26 |
1 |
|
T99 |
1 |
|
T82 |
8 |
| true |
5614 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1233 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T246 |
1 |
| others[1] |
1235 |
1 |
|
T125 |
1 |
|
T311 |
1 |
|
T313 |
1 |
| others[2] |
1263 |
1 |
|
T54 |
1 |
|
T184 |
1 |
|
T117 |
1 |
| others[3] |
2012 |
1 |
|
T53 |
1 |
|
T116 |
1 |
|
T118 |
1 |
| false |
632 |
1 |
|
T127 |
1 |
|
T350 |
1 |
|
T2 |
1 |
| true |
432 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1208 |
1 |
|
T52 |
1 |
|
T116 |
1 |
|
T311 |
1 |
| others[1] |
1276 |
1 |
|
T125 |
1 |
|
T117 |
1 |
|
T128 |
1 |
| others[2] |
1256 |
1 |
|
T120 |
1 |
|
T246 |
1 |
|
T124 |
1 |
| others[3] |
2025 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
622 |
1 |
|
T184 |
1 |
|
T248 |
1 |
|
T350 |
1 |
| true |
420 |
1 |
|
T4 |
1 |
|
T26 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
90 |
1 |
|
T82 |
6 |
|
T88 |
4 |
|
T340 |
1 |
| others[1] |
110 |
1 |
|
T20 |
1 |
|
T99 |
1 |
|
T82 |
4 |
| others[2] |
95 |
1 |
|
T82 |
1 |
|
T73 |
1 |
|
T338 |
1 |
| others[3] |
190 |
1 |
|
T82 |
6 |
|
T64 |
1 |
|
T73 |
1 |
| false |
53 |
1 |
|
T82 |
1 |
|
T339 |
1 |
|
T88 |
2 |
| true |
6269 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T23 |
1 |
| others[1] |
248 |
1 |
|
T34 |
1 |
|
T82 |
11 |
|
T235 |
1 |
| others[2] |
234 |
1 |
|
T26 |
1 |
|
T82 |
14 |
|
T57 |
1 |
| others[3] |
381 |
1 |
|
T82 |
20 |
|
T64 |
1 |
|
T27 |
1 |
| false |
111 |
1 |
|
T82 |
6 |
|
T73 |
1 |
|
T339 |
1 |
| true |
5582 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1035 |
1 |
|
T54 |
1 |
|
T247 |
1 |
|
T312 |
1 |
| others[1] |
1031 |
1 |
|
T53 |
1 |
|
T118 |
1 |
|
T300 |
1 |
| others[2] |
1074 |
1 |
|
T311 |
1 |
|
T120 |
1 |
|
T246 |
1 |
| others[3] |
1694 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T125 |
1 |
| false |
572 |
1 |
|
T343 |
1 |
|
T1 |
1 |
|
T6 |
4 |
| true |
1401 |
1 |
|
T4 |
1 |
|
T6 |
49 |
|
T34 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |