Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T82 |
10 |
|
T61 |
1 |
|
T346 |
1 |
| others[1] |
232 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T99 |
1 |
| others[2] |
217 |
1 |
|
T82 |
9 |
|
T88 |
6 |
|
T101 |
1 |
| others[3] |
361 |
1 |
|
T26 |
1 |
|
T100 |
1 |
|
T82 |
13 |
| false |
115 |
1 |
|
T4 |
1 |
|
T82 |
5 |
|
T58 |
1 |
| true |
5628 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T82 |
13 |
|
T73 |
1 |
|
T88 |
10 |
| others[1] |
231 |
1 |
|
T82 |
6 |
|
T27 |
1 |
|
T88 |
13 |
| others[2] |
216 |
1 |
|
T99 |
1 |
|
T82 |
10 |
|
T39 |
1 |
| others[3] |
366 |
1 |
|
T82 |
21 |
|
T73 |
1 |
|
T204 |
1 |
| false |
119 |
1 |
|
T82 |
5 |
|
T339 |
1 |
|
T88 |
6 |
| true |
5638 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1193 |
1 |
|
T125 |
1 |
|
T120 |
1 |
|
T122 |
1 |
| others[1] |
1244 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T247 |
1 |
| others[2] |
1257 |
1 |
|
T45 |
1 |
|
T311 |
1 |
|
T350 |
1 |
| others[3] |
2083 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T116 |
1 |
| false |
601 |
1 |
|
T347 |
1 |
|
T6 |
7 |
|
T7 |
1 |
| true |
429 |
1 |
|
T22 |
1 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1206 |
1 |
|
T45 |
1 |
|
T184 |
1 |
|
T122 |
1 |
| others[1] |
1260 |
1 |
|
T53 |
1 |
|
T118 |
1 |
|
T128 |
1 |
| others[2] |
1252 |
1 |
|
T125 |
1 |
|
T116 |
1 |
|
T252 |
1 |
| others[3] |
2033 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T311 |
1 |
| false |
640 |
1 |
|
T300 |
1 |
|
T126 |
1 |
|
T6 |
12 |
| true |
416 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T82 |
2 |
|
T339 |
1 |
|
T88 |
3 |
| others[1] |
100 |
1 |
|
T99 |
1 |
|
T82 |
1 |
|
T73 |
1 |
| others[2] |
101 |
1 |
|
T20 |
1 |
|
T82 |
3 |
|
T235 |
1 |
| others[3] |
165 |
1 |
|
T82 |
4 |
|
T73 |
1 |
|
T337 |
2 |
| false |
51 |
1 |
|
T82 |
3 |
|
T115 |
2 |
|
T89 |
1 |
| true |
6277 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T99 |
1 |
|
T82 |
12 |
|
T235 |
1 |
| others[1] |
242 |
1 |
|
T158 |
1 |
|
T100 |
1 |
|
T82 |
4 |
| others[2] |
223 |
1 |
|
T4 |
1 |
|
T82 |
4 |
|
T64 |
1 |
| others[3] |
398 |
1 |
|
T34 |
1 |
|
T82 |
15 |
|
T214 |
1 |
| false |
130 |
1 |
|
T22 |
1 |
|
T82 |
6 |
|
T88 |
7 |
| true |
5603 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1042 |
1 |
|
T52 |
1 |
|
T116 |
1 |
|
T118 |
1 |
| others[1] |
1032 |
1 |
|
T53 |
1 |
|
T124 |
1 |
|
T6 |
14 |
| others[2] |
1028 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T184 |
1 |
| others[3] |
1732 |
1 |
|
T311 |
1 |
|
T117 |
1 |
|
T120 |
1 |
| false |
554 |
1 |
|
T125 |
1 |
|
T1 |
1 |
|
T20 |
1 |
| true |
1419 |
1 |
|
T4 |
1 |
|
T6 |
53 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T82 |
11 |
|
T88 |
8 |
|
T340 |
1 |
| others[1] |
229 |
1 |
|
T22 |
1 |
|
T82 |
9 |
|
T269 |
1 |
| others[2] |
249 |
1 |
|
T82 |
9 |
|
T64 |
1 |
|
T27 |
1 |
| others[3] |
401 |
1 |
|
T82 |
12 |
|
T73 |
1 |
|
T28 |
1 |
| false |
117 |
1 |
|
T82 |
6 |
|
T106 |
1 |
|
T88 |
4 |
| true |
5583 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T100 |
1 |
|
T82 |
7 |
|
T73 |
1 |
| others[1] |
226 |
1 |
|
T82 |
5 |
|
T73 |
1 |
|
T338 |
1 |
| others[2] |
229 |
1 |
|
T82 |
11 |
|
T88 |
12 |
|
T89 |
13 |
| others[3] |
370 |
1 |
|
T99 |
1 |
|
T82 |
21 |
|
T88 |
22 |
| false |
118 |
1 |
|
T82 |
3 |
|
T88 |
5 |
|
T342 |
1 |
| true |
5630 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1189 |
1 |
|
T45 |
1 |
|
T184 |
1 |
|
T6 |
17 |
| others[1] |
1213 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[2] |
1214 |
1 |
|
T120 |
1 |
|
T122 |
1 |
|
T343 |
1 |
| others[3] |
2097 |
1 |
|
T125 |
1 |
|
T116 |
1 |
|
T117 |
1 |
| false |
642 |
1 |
|
T20 |
1 |
|
T6 |
12 |
|
T7 |
1 |
| true |
452 |
1 |
|
T34 |
1 |
|
T26 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T54 |
1 |
|
T116 |
1 |
|
T118 |
1 |
| others[1] |
1230 |
1 |
|
T53 |
1 |
|
T311 |
1 |
|
T246 |
1 |
| others[2] |
1216 |
1 |
|
T45 |
1 |
|
T184 |
1 |
|
T117 |
1 |
| others[3] |
2064 |
1 |
|
T52 |
1 |
|
T248 |
1 |
|
T312 |
1 |
| false |
607 |
1 |
|
T125 |
1 |
|
T20 |
1 |
|
T6 |
7 |
| true |
420 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T82 |
4 |
|
T73 |
1 |
|
T339 |
1 |
| others[1] |
92 |
1 |
|
T82 |
7 |
|
T88 |
5 |
|
T101 |
1 |
| others[2] |
106 |
1 |
|
T82 |
4 |
|
T204 |
1 |
|
T88 |
1 |
| others[3] |
164 |
1 |
|
T20 |
1 |
|
T99 |
1 |
|
T82 |
9 |
| false |
57 |
1 |
|
T82 |
2 |
|
T88 |
3 |
|
T89 |
4 |
| true |
6281 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
268 |
1 |
|
T22 |
1 |
|
T82 |
7 |
|
T61 |
1 |
| others[1] |
217 |
1 |
|
T158 |
1 |
|
T82 |
12 |
|
T339 |
1 |
| others[2] |
250 |
1 |
|
T99 |
1 |
|
T82 |
9 |
|
T27 |
1 |
| others[3] |
357 |
1 |
|
T34 |
1 |
|
T23 |
1 |
|
T82 |
12 |
| false |
90 |
1 |
|
T82 |
7 |
|
T235 |
1 |
|
T88 |
5 |
| true |
5625 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1007 |
1 |
|
T125 |
1 |
|
T184 |
1 |
|
T311 |
1 |
| others[1] |
1038 |
1 |
|
T52 |
1 |
|
T116 |
1 |
|
T117 |
1 |
| others[2] |
1059 |
1 |
|
T45 |
1 |
|
T246 |
1 |
|
T122 |
1 |
| others[3] |
1787 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T118 |
1 |
| false |
511 |
1 |
|
T314 |
1 |
|
T6 |
3 |
|
T30 |
7 |
| true |
1405 |
1 |
|
T4 |
1 |
|
T6 |
52 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T4 |
1 |
|
T99 |
1 |
|
T82 |
6 |
| others[1] |
228 |
1 |
|
T82 |
8 |
|
T27 |
1 |
|
T339 |
1 |
| others[2] |
219 |
1 |
|
T82 |
11 |
|
T204 |
1 |
|
T338 |
1 |
| others[3] |
406 |
1 |
|
T82 |
20 |
|
T39 |
1 |
|
T269 |
1 |
| false |
102 |
1 |
|
T82 |
1 |
|
T345 |
1 |
|
T88 |
5 |
| true |
5625 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T82 |
13 |
|
T64 |
1 |
|
T73 |
1 |
| others[1] |
210 |
1 |
|
T82 |
7 |
|
T235 |
1 |
|
T341 |
1 |
| others[2] |
233 |
1 |
|
T82 |
9 |
|
T27 |
1 |
|
T88 |
13 |
| others[3] |
393 |
1 |
|
T99 |
1 |
|
T82 |
13 |
|
T339 |
1 |
| false |
105 |
1 |
|
T20 |
1 |
|
T82 |
8 |
|
T338 |
1 |
| true |
5650 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T125 |
1 |
|
T184 |
1 |
|
T311 |
1 |
| others[1] |
1216 |
1 |
|
T122 |
1 |
|
T248 |
1 |
|
T252 |
1 |
| others[2] |
1292 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T312 |
1 |
| others[3] |
2011 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T116 |
1 |
| false |
627 |
1 |
|
T126 |
1 |
|
T343 |
1 |
|
T347 |
1 |
| true |
433 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1249 |
1 |
|
T311 |
1 |
|
T252 |
1 |
|
T126 |
1 |
| others[1] |
1176 |
1 |
|
T53 |
1 |
|
T117 |
1 |
|
T124 |
1 |
| others[2] |
1244 |
1 |
|
T247 |
1 |
|
T300 |
1 |
|
T6 |
20 |
| others[3] |
2071 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T184 |
1 |
| false |
641 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T246 |
1 |
| true |
426 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T20 |
1 |
|
T26 |
1 |
|
T82 |
1 |
| others[1] |
115 |
1 |
|
T82 |
5 |
|
T88 |
5 |
|
T115 |
2 |
| others[2] |
100 |
1 |
|
T99 |
1 |
|
T82 |
3 |
|
T235 |
1 |
| others[3] |
165 |
1 |
|
T82 |
3 |
|
T27 |
1 |
|
T73 |
1 |
| false |
61 |
1 |
|
T82 |
1 |
|
T73 |
1 |
|
T88 |
3 |
| true |
6268 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T4 |
1 |
|
T82 |
7 |
|
T88 |
7 |
| others[1] |
228 |
1 |
|
T26 |
1 |
|
T100 |
1 |
|
T82 |
13 |
| others[2] |
246 |
1 |
|
T82 |
7 |
|
T338 |
1 |
|
T65 |
1 |
| others[3] |
439 |
1 |
|
T34 |
1 |
|
T158 |
1 |
|
T82 |
20 |
| false |
126 |
1 |
|
T99 |
1 |
|
T82 |
5 |
|
T73 |
1 |
| true |
5562 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1078 |
1 |
|
T118 |
1 |
|
T246 |
1 |
|
T247 |
1 |
| others[1] |
1014 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T125 |
1 |
| others[2] |
1068 |
1 |
|
T120 |
1 |
|
T6 |
6 |
|
T34 |
1 |
| others[3] |
1718 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T184 |
1 |
| false |
577 |
1 |
|
T311 |
1 |
|
T122 |
1 |
|
T6 |
6 |
| true |
1352 |
1 |
|
T6 |
44 |
|
T22 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T82 |
6 |
|
T39 |
1 |
|
T269 |
1 |
| others[1] |
230 |
1 |
|
T20 |
1 |
|
T100 |
1 |
|
T82 |
13 |
| others[2] |
246 |
1 |
|
T26 |
1 |
|
T23 |
1 |
|
T99 |
1 |
| others[3] |
365 |
1 |
|
T82 |
18 |
|
T88 |
11 |
|
T351 |
1 |
| false |
106 |
1 |
|
T82 |
7 |
|
T339 |
1 |
|
T28 |
1 |
| true |
5612 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T82 |
10 |
|
T88 |
13 |
|
T89 |
10 |
| others[1] |
228 |
1 |
|
T82 |
12 |
|
T73 |
1 |
|
T339 |
1 |
| others[2] |
237 |
1 |
|
T158 |
1 |
|
T82 |
8 |
|
T28 |
1 |
| others[3] |
358 |
1 |
|
T23 |
1 |
|
T99 |
1 |
|
T82 |
20 |
| false |
112 |
1 |
|
T82 |
7 |
|
T64 |
1 |
|
T338 |
1 |
| true |
5656 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1296 |
1 |
|
T184 |
1 |
|
T116 |
1 |
|
T311 |
1 |
| others[1] |
1219 |
1 |
|
T125 |
1 |
|
T246 |
1 |
|
T122 |
1 |
| others[2] |
1179 |
1 |
|
T45 |
1 |
|
T247 |
1 |
|
T300 |
1 |
| others[3] |
2030 |
1 |
|
T52 |
1 |
|
T120 |
1 |
|
T252 |
1 |
| false |
640 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T343 |
1 |
| true |
443 |
1 |
|
T22 |
1 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1250 |
1 |
|
T116 |
1 |
|
T120 |
1 |
|
T124 |
1 |
| others[1] |
1206 |
1 |
|
T184 |
1 |
|
T246 |
1 |
|
T312 |
1 |
| others[2] |
1276 |
1 |
|
T45 |
1 |
|
T118 |
1 |
|
T122 |
1 |
| others[3] |
2012 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T311 |
1 |
| false |
640 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T127 |
1 |
| true |
423 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
118 |
1 |
|
T99 |
1 |
|
T82 |
7 |
|
T339 |
1 |
| others[1] |
93 |
1 |
|
T158 |
1 |
|
T82 |
1 |
|
T88 |
4 |
| others[2] |
106 |
1 |
|
T82 |
3 |
|
T73 |
1 |
|
T235 |
1 |
| others[3] |
175 |
1 |
|
T82 |
5 |
|
T341 |
1 |
|
T338 |
1 |
| false |
57 |
1 |
|
T20 |
1 |
|
T82 |
1 |
|
T64 |
1 |
| true |
6258 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T82 |
8 |
|
T61 |
1 |
|
T27 |
1 |
| others[1] |
252 |
1 |
|
T20 |
1 |
|
T82 |
15 |
|
T203 |
1 |
| others[2] |
212 |
1 |
|
T82 |
6 |
|
T73 |
1 |
|
T235 |
1 |
| others[3] |
391 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T158 |
1 |
| false |
120 |
1 |
|
T99 |
1 |
|
T82 |
4 |
|
T107 |
1 |
| true |
5594 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1030 |
1 |
|
T54 |
1 |
|
T246 |
1 |
|
T248 |
1 |
| others[1] |
1028 |
1 |
|
T184 |
1 |
|
T122 |
1 |
|
T124 |
1 |
| others[2] |
1020 |
1 |
|
T125 |
1 |
|
T117 |
1 |
|
T118 |
1 |
| others[3] |
1776 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
| false |
525 |
1 |
|
T116 |
1 |
|
T314 |
1 |
|
T1 |
1 |
| true |
1428 |
1 |
|
T4 |
1 |
|
T6 |
50 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T82 |
11 |
|
T346 |
1 |
|
T88 |
12 |
| others[1] |
241 |
1 |
|
T82 |
10 |
|
T39 |
1 |
|
T235 |
1 |
| others[2] |
222 |
1 |
|
T82 |
8 |
|
T64 |
1 |
|
T337 |
1 |
| others[3] |
391 |
1 |
|
T26 |
1 |
|
T158 |
1 |
|
T82 |
13 |
| false |
123 |
1 |
|
T82 |
11 |
|
T88 |
5 |
|
T89 |
10 |
| true |
5616 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T82 |
11 |
|
T339 |
1 |
|
T345 |
1 |
| others[1] |
217 |
1 |
|
T26 |
1 |
|
T82 |
8 |
|
T341 |
1 |
| others[2] |
215 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T82 |
12 |
| others[3] |
376 |
1 |
|
T82 |
19 |
|
T338 |
1 |
|
T337 |
1 |
| false |
100 |
1 |
|
T158 |
1 |
|
T100 |
1 |
|
T82 |
4 |
| true |
5661 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1183 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T116 |
1 |
| others[1] |
1216 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T247 |
1 |
| others[2] |
1260 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T117 |
1 |
| others[3] |
2103 |
1 |
|
T311 |
1 |
|
T246 |
1 |
|
T122 |
1 |
| false |
605 |
1 |
|
T248 |
1 |
|
T6 |
11 |
|
T25 |
1 |
| true |
440 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |