Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1208 |
1 |
|
T117 |
1 |
|
T122 |
1 |
|
T247 |
1 |
| others[1] |
1181 |
1 |
|
T53 |
1 |
|
T184 |
1 |
|
T246 |
1 |
| others[2] |
1299 |
1 |
|
T311 |
1 |
|
T300 |
1 |
|
T126 |
1 |
| others[3] |
2104 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T54 |
1 |
| false |
602 |
1 |
|
T6 |
7 |
|
T30 |
11 |
|
T42 |
1 |
| true |
413 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T82 |
6 |
|
T73 |
1 |
|
T338 |
1 |
| others[1] |
100 |
1 |
|
T82 |
6 |
|
T337 |
2 |
|
T88 |
4 |
| others[2] |
88 |
1 |
|
T99 |
1 |
|
T82 |
8 |
|
T64 |
1 |
| others[3] |
156 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T82 |
4 |
| false |
61 |
1 |
|
T82 |
2 |
|
T88 |
2 |
|
T89 |
2 |
| true |
6287 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T82 |
8 |
|
T39 |
1 |
|
T339 |
1 |
| others[1] |
226 |
1 |
|
T82 |
14 |
|
T61 |
1 |
|
T348 |
1 |
| others[2] |
237 |
1 |
|
T82 |
13 |
|
T64 |
1 |
|
T269 |
1 |
| others[3] |
398 |
1 |
|
T20 |
1 |
|
T26 |
1 |
|
T100 |
1 |
| false |
127 |
1 |
|
T82 |
1 |
|
T235 |
1 |
|
T341 |
1 |
| true |
5586 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1050 |
1 |
|
T125 |
1 |
|
T300 |
1 |
|
T1 |
1 |
| others[1] |
1015 |
1 |
|
T45 |
1 |
|
T184 |
1 |
|
T311 |
1 |
| others[2] |
1081 |
1 |
|
T118 |
1 |
|
T246 |
1 |
|
T248 |
1 |
| others[3] |
1713 |
1 |
|
T53 |
1 |
|
T247 |
1 |
|
T124 |
1 |
| false |
545 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T116 |
1 |
| true |
1403 |
1 |
|
T6 |
48 |
|
T22 |
1 |
|
T30 |
36 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T20 |
1 |
|
T99 |
1 |
|
T82 |
12 |
| others[1] |
244 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T82 |
7 |
| others[2] |
226 |
1 |
|
T26 |
1 |
|
T82 |
9 |
|
T27 |
1 |
| others[3] |
381 |
1 |
|
T82 |
15 |
|
T88 |
21 |
|
T62 |
1 |
| false |
116 |
1 |
|
T82 |
4 |
|
T348 |
1 |
|
T88 |
7 |
| true |
5599 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T20 |
1 |
|
T82 |
13 |
|
T337 |
1 |
| others[1] |
200 |
1 |
|
T82 |
5 |
|
T339 |
1 |
|
T341 |
1 |
| others[2] |
216 |
1 |
|
T82 |
17 |
|
T28 |
1 |
|
T88 |
10 |
| others[3] |
378 |
1 |
|
T23 |
1 |
|
T82 |
12 |
|
T73 |
1 |
| false |
129 |
1 |
|
T82 |
5 |
|
T88 |
8 |
|
T115 |
1 |
| true |
5678 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T52 |
1 |
|
T117 |
1 |
|
T120 |
1 |
| others[1] |
1239 |
1 |
|
T300 |
1 |
|
T126 |
1 |
|
T127 |
1 |
| others[2] |
1185 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T184 |
1 |
| others[3] |
2049 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T311 |
1 |
| false |
653 |
1 |
|
T116 |
1 |
|
T247 |
1 |
|
T2 |
1 |
| true |
440 |
1 |
|
T22 |
1 |
|
T34 |
1 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T54 |
1 |
| others[1] |
1229 |
1 |
|
T53 |
1 |
|
T116 |
1 |
|
T117 |
1 |
| others[2] |
1234 |
1 |
|
T184 |
1 |
|
T2 |
1 |
|
T6 |
17 |
| others[3] |
2056 |
1 |
|
T118 |
1 |
|
T246 |
1 |
|
T247 |
1 |
| false |
635 |
1 |
|
T120 |
1 |
|
T347 |
1 |
|
T6 |
8 |
| true |
427 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T82 |
3 |
|
T64 |
1 |
|
T73 |
1 |
| others[1] |
109 |
1 |
|
T99 |
1 |
|
T82 |
5 |
|
T73 |
1 |
| others[2] |
97 |
1 |
|
T82 |
5 |
|
T235 |
1 |
|
T338 |
1 |
| others[3] |
186 |
1 |
|
T20 |
1 |
|
T82 |
2 |
|
T339 |
1 |
| false |
50 |
1 |
|
T82 |
2 |
|
T88 |
4 |
|
T89 |
1 |
| true |
6262 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T158 |
1 |
|
T82 |
6 |
|
T271 |
1 |
| others[1] |
228 |
1 |
|
T82 |
11 |
|
T73 |
1 |
|
T338 |
1 |
| others[2] |
207 |
1 |
|
T26 |
1 |
|
T82 |
16 |
|
T73 |
1 |
| others[3] |
382 |
1 |
|
T20 |
1 |
|
T82 |
15 |
|
T57 |
1 |
| false |
138 |
1 |
|
T82 |
3 |
|
T337 |
1 |
|
T88 |
6 |
| true |
5641 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1018 |
1 |
|
T125 |
1 |
|
T2 |
1 |
|
T20 |
1 |
| others[1] |
971 |
1 |
|
T53 |
1 |
|
T120 |
1 |
|
T122 |
1 |
| others[2] |
1116 |
1 |
|
T52 |
1 |
|
T116 |
1 |
|
T311 |
1 |
| others[3] |
1761 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T184 |
1 |
| false |
528 |
1 |
|
T124 |
1 |
|
T126 |
1 |
|
T6 |
5 |
| true |
1413 |
1 |
|
T6 |
44 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T20 |
1 |
|
T82 |
16 |
|
T61 |
1 |
| others[1] |
214 |
1 |
|
T82 |
10 |
|
T88 |
6 |
|
T62 |
1 |
| others[2] |
223 |
1 |
|
T82 |
10 |
|
T269 |
1 |
|
T88 |
8 |
| others[3] |
391 |
1 |
|
T100 |
1 |
|
T82 |
12 |
|
T64 |
1 |
| false |
124 |
1 |
|
T82 |
5 |
|
T88 |
9 |
|
T352 |
1 |
| true |
5614 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T82 |
7 |
|
T27 |
1 |
|
T341 |
1 |
| others[1] |
234 |
1 |
|
T26 |
1 |
|
T23 |
1 |
|
T82 |
9 |
| others[2] |
217 |
1 |
|
T82 |
3 |
|
T338 |
1 |
|
T88 |
7 |
| others[3] |
350 |
1 |
|
T20 |
1 |
|
T82 |
21 |
|
T39 |
1 |
| false |
127 |
1 |
|
T82 |
6 |
|
T88 |
10 |
|
T89 |
6 |
| true |
5644 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1278 |
1 |
|
T116 |
1 |
|
T311 |
1 |
|
T117 |
1 |
| others[1] |
1228 |
1 |
|
T125 |
1 |
|
T246 |
1 |
|
T127 |
1 |
| others[2] |
1186 |
1 |
|
T52 |
1 |
|
T120 |
1 |
|
T122 |
1 |
| others[3] |
2019 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T184 |
1 |
| false |
661 |
1 |
|
T54 |
1 |
|
T247 |
1 |
|
T126 |
1 |
| true |
435 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T117 |
1 |
| others[1] |
1209 |
1 |
|
T54 |
1 |
|
T116 |
1 |
|
T246 |
1 |
| others[2] |
1253 |
1 |
|
T52 |
1 |
|
T120 |
1 |
|
T6 |
18 |
| others[3] |
2043 |
1 |
|
T184 |
1 |
|
T118 |
1 |
|
T122 |
1 |
| false |
638 |
1 |
|
T125 |
1 |
|
T311 |
1 |
|
T247 |
1 |
| true |
424 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T20 |
1 |
|
T82 |
4 |
|
T338 |
1 |
| others[1] |
108 |
1 |
|
T26 |
1 |
|
T82 |
3 |
|
T73 |
1 |
| others[2] |
100 |
1 |
|
T82 |
4 |
|
T64 |
1 |
|
T73 |
1 |
| others[3] |
171 |
1 |
|
T82 |
5 |
|
T337 |
1 |
|
T88 |
7 |
| false |
60 |
1 |
|
T99 |
1 |
|
T338 |
1 |
|
T88 |
1 |
| true |
6263 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
265 |
1 |
|
T4 |
1 |
|
T82 |
9 |
|
T344 |
1 |
| others[1] |
215 |
1 |
|
T23 |
1 |
|
T82 |
9 |
|
T61 |
1 |
| others[2] |
250 |
1 |
|
T82 |
7 |
|
T28 |
1 |
|
T345 |
1 |
| others[3] |
384 |
1 |
|
T22 |
1 |
|
T26 |
1 |
|
T158 |
1 |
| false |
118 |
1 |
|
T82 |
1 |
|
T214 |
1 |
|
T269 |
1 |
| true |
5575 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1026 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T118 |
1 |
| others[1] |
1086 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| others[2] |
1043 |
1 |
|
T124 |
1 |
|
T350 |
1 |
|
T2 |
1 |
| others[3] |
1745 |
1 |
|
T116 |
1 |
|
T311 |
1 |
|
T246 |
1 |
| false |
522 |
1 |
|
T117 |
1 |
|
T347 |
1 |
|
T314 |
1 |
| true |
1385 |
1 |
|
T6 |
50 |
|
T26 |
1 |
|
T30 |
24 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T82 |
10 |
|
T28 |
1 |
|
T271 |
1 |
| others[1] |
225 |
1 |
|
T4 |
1 |
|
T158 |
1 |
|
T82 |
16 |
| others[2] |
225 |
1 |
|
T82 |
7 |
|
T73 |
1 |
|
T106 |
1 |
| others[3] |
377 |
1 |
|
T22 |
1 |
|
T82 |
15 |
|
T344 |
1 |
| false |
123 |
1 |
|
T82 |
5 |
|
T88 |
5 |
|
T115 |
1 |
| true |
5627 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
218 |
1 |
|
T20 |
1 |
|
T82 |
10 |
|
T339 |
1 |
| others[1] |
219 |
1 |
|
T82 |
11 |
|
T64 |
1 |
|
T28 |
1 |
| others[2] |
228 |
1 |
|
T82 |
13 |
|
T27 |
1 |
|
T73 |
1 |
| others[3] |
404 |
1 |
|
T23 |
1 |
|
T82 |
19 |
|
T235 |
1 |
| false |
100 |
1 |
|
T82 |
3 |
|
T341 |
1 |
|
T338 |
1 |
| true |
5638 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T116 |
1 |
|
T118 |
1 |
|
T122 |
1 |
| others[1] |
1216 |
1 |
|
T311 |
1 |
|
T246 |
1 |
|
T247 |
1 |
| others[2] |
1229 |
1 |
|
T52 |
1 |
|
T117 |
1 |
|
T120 |
1 |
| others[3] |
2039 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| false |
659 |
1 |
|
T53 |
1 |
|
T184 |
1 |
|
T124 |
1 |
| true |
444 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1214 |
1 |
|
T184 |
1 |
|
T117 |
1 |
|
T122 |
1 |
| others[1] |
1234 |
1 |
|
T53 |
1 |
|
T116 |
1 |
|
T311 |
1 |
| others[2] |
1296 |
1 |
|
T45 |
1 |
|
T120 |
1 |
|
T252 |
1 |
| others[3] |
2014 |
1 |
|
T54 |
1 |
|
T125 |
1 |
|
T247 |
1 |
| false |
626 |
1 |
|
T52 |
1 |
|
T246 |
1 |
|
T127 |
1 |
| true |
423 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T82 |
7 |
|
T338 |
1 |
|
T337 |
1 |
| others[1] |
99 |
1 |
|
T20 |
1 |
|
T82 |
4 |
|
T73 |
1 |
| others[2] |
109 |
1 |
|
T82 |
8 |
|
T28 |
1 |
|
T337 |
1 |
| others[3] |
160 |
1 |
|
T99 |
1 |
|
T82 |
6 |
|
T73 |
1 |
| false |
57 |
1 |
|
T82 |
1 |
|
T339 |
1 |
|
T345 |
1 |
| true |
6281 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T22 |
1 |
|
T82 |
12 |
|
T73 |
1 |
| others[1] |
251 |
1 |
|
T82 |
8 |
|
T205 |
1 |
|
T348 |
1 |
| others[2] |
231 |
1 |
|
T34 |
1 |
|
T23 |
1 |
|
T82 |
9 |
| others[3] |
386 |
1 |
|
T20 |
1 |
|
T82 |
14 |
|
T64 |
1 |
| false |
122 |
1 |
|
T26 |
1 |
|
T82 |
6 |
|
T269 |
1 |
| true |
5574 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1057 |
1 |
|
T116 |
1 |
|
T247 |
1 |
|
T126 |
1 |
| others[1] |
967 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T311 |
1 |
| others[2] |
1052 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[3] |
1803 |
1 |
|
T184 |
1 |
|
T252 |
1 |
|
T124 |
1 |
| false |
541 |
1 |
|
T117 |
1 |
|
T118 |
1 |
|
T246 |
1 |
| true |
1387 |
1 |
|
T4 |
1 |
|
T6 |
41 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T82 |
7 |
|
T337 |
1 |
|
T106 |
1 |
| others[1] |
216 |
1 |
|
T23 |
1 |
|
T99 |
1 |
|
T82 |
13 |
| others[2] |
214 |
1 |
|
T82 |
10 |
|
T61 |
1 |
|
T73 |
1 |
| others[3] |
390 |
1 |
|
T20 |
1 |
|
T82 |
16 |
|
T64 |
1 |
| false |
128 |
1 |
|
T100 |
1 |
|
T82 |
6 |
|
T344 |
1 |
| true |
5646 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T26 |
1 |
|
T82 |
11 |
|
T339 |
1 |
| others[1] |
211 |
1 |
|
T82 |
8 |
|
T73 |
1 |
|
T345 |
1 |
| others[2] |
239 |
1 |
|
T23 |
1 |
|
T99 |
1 |
|
T82 |
8 |
| others[3] |
352 |
1 |
|
T20 |
1 |
|
T82 |
19 |
|
T39 |
1 |
| false |
114 |
1 |
|
T82 |
6 |
|
T338 |
1 |
|
T88 |
9 |
| true |
5674 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1195 |
1 |
|
T53 |
1 |
|
T117 |
1 |
|
T246 |
1 |
| others[1] |
1241 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T184 |
1 |
| others[2] |
1218 |
1 |
|
T125 |
1 |
|
T118 |
1 |
|
T248 |
1 |
| others[3] |
2082 |
1 |
|
T45 |
1 |
|
T252 |
1 |
|
T124 |
1 |
| false |
635 |
1 |
|
T300 |
1 |
|
T6 |
9 |
|
T30 |
4 |
| true |
436 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
14 |
1 |
|
T74 |
1 |
|
T155 |
1 |
|
T161 |
1 |
| others[1] |
3 |
1 |
|
T353 |
1 |
|
T354 |
1 |
|
T355 |
1 |
| others[2] |
9 |
1 |
|
T356 |
1 |
|
T354 |
1 |
|
T163 |
1 |
| others[3] |
10 |
1 |
|
T156 |
1 |
|
T148 |
1 |
|
T357 |
1 |
| false |
5 |
1 |
|
T358 |
1 |
|
T359 |
1 |
|
T360 |
1 |
| true |
50 |
1 |
|
T13 |
1 |
|
T133 |
1 |
|
T156 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
3 |
1 |
|
T41 |
1 |
|
T361 |
1 |
|
T362 |
1 |
| others[1] |
2 |
1 |
|
T175 |
1 |
|
T363 |
1 |
|
- |
- |
| others[2] |
5 |
1 |
|
T364 |
1 |
|
T365 |
1 |
|
T366 |
1 |
| others[3] |
3 |
1 |
|
T367 |
1 |
|
T368 |
1 |
|
T369 |
1 |
| false |
14 |
1 |
|
T331 |
1 |
|
T370 |
1 |
|
T371 |
1 |
| true |
22 |
1 |
|
T5 |
1 |
|
T8 |
1 |
|
T176 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T8 |
1 |
|
T367 |
1 |
|
T370 |
1 |
| others[1] |
2 |
1 |
|
T372 |
1 |
|
T373 |
1 |
|
- |
- |
| others[2] |
2 |
1 |
|
T374 |
1 |
|
T375 |
1 |
|
- |
- |
| others[3] |
5 |
1 |
|
T363 |
1 |
|
T376 |
1 |
|
T377 |
1 |
| false |
11 |
1 |
|
T41 |
1 |
|
T362 |
1 |
|
T378 |
1 |
| true |
25 |
1 |
|
T5 |
1 |
|
T331 |
1 |
|
T175 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |