Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9855 |
1 |
|
T117 |
1 |
|
T118 |
1 |
|
T122 |
1 |
| others[1] |
818 |
1 |
|
T53 |
1 |
|
T184 |
1 |
|
T116 |
1 |
| others[2] |
761 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T126 |
1 |
| others[3] |
1287 |
1 |
|
T54 |
1 |
|
T120 |
1 |
|
T247 |
1 |
| false |
389 |
1 |
|
T45 |
1 |
|
T311 |
1 |
|
T124 |
1 |
| true |
512 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2327 |
1 |
|
T52 |
1 |
|
T118 |
1 |
|
T120 |
1 |
| others[1] |
2246 |
1 |
|
T311 |
1 |
|
T248 |
1 |
|
T252 |
1 |
| others[2] |
2251 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T117 |
1 |
| others[3] |
3975 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T116 |
1 |
| false |
1268 |
1 |
|
T184 |
1 |
|
T122 |
1 |
|
T126 |
1 |
| true |
1555 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9346 |
1 |
|
T52 |
1 |
|
T6 |
100 |
|
T30 |
62 |
| others[1] |
257 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T1 |
1 |
| others[2] |
297 |
1 |
|
T116 |
1 |
|
T120 |
1 |
|
T343 |
1 |
| others[3] |
427 |
1 |
|
T117 |
1 |
|
T248 |
1 |
|
T347 |
1 |
| false |
143 |
1 |
|
T34 |
1 |
|
T26 |
1 |
|
T82 |
7 |
| true |
3152 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9539 |
1 |
|
T184 |
1 |
|
T246 |
1 |
|
T127 |
1 |
| others[1] |
473 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T120 |
1 |
| others[2] |
441 |
1 |
|
T118 |
1 |
|
T12 |
1 |
|
T42 |
1 |
| others[3] |
790 |
1 |
|
T122 |
1 |
|
T248 |
1 |
|
T1 |
1 |
| false |
218 |
1 |
|
T53 |
1 |
|
T126 |
1 |
|
T343 |
1 |
| true |
2161 |
1 |
|
T54 |
1 |
|
T125 |
1 |
|
T116 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9318 |
1 |
|
T53 |
1 |
|
T116 |
1 |
|
T120 |
1 |
| others[1] |
262 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T311 |
1 |
| others[2] |
269 |
1 |
|
T122 |
1 |
|
T314 |
1 |
|
T82 |
18 |
| others[3] |
445 |
1 |
|
T118 |
1 |
|
T124 |
1 |
|
T23 |
1 |
| false |
128 |
1 |
|
T2 |
1 |
|
T21 |
1 |
|
T82 |
3 |
| true |
3200 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9329 |
1 |
|
T247 |
1 |
|
T312 |
1 |
|
T127 |
1 |
| others[1] |
267 |
1 |
|
T52 |
1 |
|
T117 |
1 |
|
T118 |
1 |
| others[2] |
247 |
1 |
|
T120 |
1 |
|
T26 |
1 |
|
T82 |
6 |
| others[3] |
389 |
1 |
|
T125 |
1 |
|
T246 |
1 |
|
T252 |
1 |
| false |
117 |
1 |
|
T116 |
1 |
|
T100 |
1 |
|
T82 |
3 |
| true |
3273 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9857 |
1 |
|
T54 |
1 |
|
T246 |
1 |
|
T128 |
1 |
| others[1] |
765 |
1 |
|
T125 |
1 |
|
T116 |
1 |
|
T118 |
1 |
| others[2] |
819 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T120 |
1 |
| others[3] |
1299 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T311 |
1 |
| false |
403 |
1 |
|
T124 |
1 |
|
T347 |
1 |
|
T25 |
2 |
| true |
479 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9833 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T311 |
1 |
| others[1] |
773 |
1 |
|
T116 |
1 |
|
T312 |
1 |
|
T126 |
1 |
| others[2] |
744 |
1 |
|
T313 |
1 |
|
T347 |
1 |
|
T82 |
22 |
| others[3] |
1333 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T125 |
1 |
| false |
415 |
1 |
|
T184 |
1 |
|
T122 |
1 |
|
T82 |
13 |
| true |
502 |
1 |
|
T4 |
1 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2274 |
1 |
|
T116 |
1 |
|
T120 |
1 |
|
T247 |
1 |
| others[1] |
2344 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T311 |
1 |
| others[2] |
2346 |
1 |
|
T125 |
1 |
|
T122 |
1 |
|
T124 |
1 |
| others[3] |
3888 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
1208 |
1 |
|
T6 |
13 |
|
T30 |
4 |
|
T82 |
6 |
| true |
1540 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9338 |
1 |
|
T125 |
1 |
|
T117 |
1 |
|
T246 |
1 |
| others[1] |
260 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T116 |
1 |
| others[2] |
249 |
1 |
|
T120 |
1 |
|
T122 |
1 |
|
T247 |
1 |
| others[3] |
444 |
1 |
|
T350 |
1 |
|
T4 |
1 |
|
T82 |
15 |
| false |
164 |
1 |
|
T343 |
1 |
|
T23 |
1 |
|
T82 |
11 |
| true |
3145 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9518 |
1 |
|
T54 |
1 |
|
T311 |
1 |
|
T120 |
1 |
| others[1] |
450 |
1 |
|
T53 |
1 |
|
T246 |
1 |
|
T82 |
11 |
| others[2] |
469 |
1 |
|
T45 |
1 |
|
T124 |
1 |
|
T23 |
1 |
| others[3] |
764 |
1 |
|
T118 |
1 |
|
T2 |
1 |
|
T20 |
1 |
| false |
243 |
1 |
|
T122 |
1 |
|
T252 |
1 |
|
T1 |
1 |
| true |
2156 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9324 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T54 |
1 |
| others[1] |
267 |
1 |
|
T184 |
1 |
|
T23 |
1 |
|
T82 |
5 |
| others[2] |
242 |
1 |
|
T117 |
1 |
|
T312 |
1 |
|
T1 |
1 |
| others[3] |
435 |
1 |
|
T120 |
1 |
|
T128 |
1 |
|
T2 |
1 |
| false |
130 |
1 |
|
T118 |
1 |
|
T21 |
1 |
|
T82 |
10 |
| true |
3202 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T116 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9298 |
1 |
|
T116 |
1 |
|
T117 |
1 |
|
T120 |
1 |
| others[1] |
266 |
1 |
|
T248 |
1 |
|
T126 |
1 |
|
T350 |
1 |
| others[2] |
220 |
1 |
|
T312 |
1 |
|
T82 |
7 |
|
T73 |
1 |
| others[3] |
425 |
1 |
|
T125 |
1 |
|
T247 |
1 |
|
T252 |
1 |
| false |
140 |
1 |
|
T314 |
1 |
|
T82 |
1 |
|
T27 |
1 |
| true |
3251 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9808 |
1 |
|
T246 |
1 |
|
T347 |
1 |
|
T1 |
1 |
| others[1] |
778 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[2] |
737 |
1 |
|
T120 |
1 |
|
T312 |
1 |
|
T313 |
1 |
| others[3] |
1385 |
1 |
|
T52 |
1 |
|
T118 |
1 |
|
T247 |
1 |
| false |
390 |
1 |
|
T248 |
1 |
|
T252 |
1 |
|
T127 |
1 |
| true |
502 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9864 |
1 |
|
T125 |
1 |
|
T311 |
1 |
|
T246 |
1 |
| others[1] |
766 |
1 |
|
T53 |
1 |
|
T117 |
1 |
|
T312 |
1 |
| others[2] |
791 |
1 |
|
T184 |
1 |
|
T300 |
1 |
|
T126 |
1 |
| others[3] |
1286 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T54 |
1 |
| false |
390 |
1 |
|
T118 |
1 |
|
T82 |
6 |
|
T172 |
6 |
| true |
503 |
1 |
|
T22 |
1 |
|
T34 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2359 |
1 |
|
T52 |
1 |
|
T120 |
1 |
|
T247 |
1 |
| others[1] |
2337 |
1 |
|
T184 |
1 |
|
T117 |
1 |
|
T118 |
1 |
| others[2] |
2336 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T347 |
1 |
| others[3] |
3862 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T116 |
1 |
| false |
1195 |
1 |
|
T311 |
1 |
|
T246 |
1 |
|
T252 |
1 |
| true |
1511 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9343 |
1 |
|
T117 |
1 |
|
T127 |
1 |
|
T343 |
1 |
| others[1] |
314 |
1 |
|
T184 |
1 |
|
T82 |
16 |
|
T64 |
1 |
| others[2] |
261 |
1 |
|
T248 |
1 |
|
T20 |
1 |
|
T7 |
1 |
| others[3] |
456 |
1 |
|
T116 |
1 |
|
T120 |
1 |
|
T247 |
1 |
| false |
152 |
1 |
|
T53 |
1 |
|
T82 |
5 |
|
T203 |
1 |
| true |
3074 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9508 |
1 |
|
T311 |
1 |
|
T117 |
1 |
|
T124 |
1 |
| others[1] |
456 |
1 |
|
T45 |
1 |
|
T2 |
1 |
|
T82 |
9 |
| others[2] |
444 |
1 |
|
T343 |
1 |
|
T347 |
1 |
|
T34 |
1 |
| others[3] |
788 |
1 |
|
T54 |
1 |
|
T120 |
1 |
|
T1 |
1 |
| false |
252 |
1 |
|
T246 |
1 |
|
T252 |
1 |
|
T312 |
1 |
| true |
2152 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T125 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9303 |
1 |
|
T53 |
1 |
|
T248 |
1 |
|
T126 |
1 |
| others[1] |
251 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T247 |
1 |
| others[2] |
252 |
1 |
|
T52 |
1 |
|
T127 |
1 |
|
T128 |
1 |
| others[3] |
490 |
1 |
|
T120 |
1 |
|
T124 |
1 |
|
T300 |
1 |
| false |
129 |
1 |
|
T246 |
1 |
|
T42 |
1 |
|
T82 |
3 |
| true |
3175 |
1 |
|
T54 |
1 |
|
T184 |
1 |
|
T116 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9298 |
1 |
|
T45 |
1 |
|
T126 |
1 |
|
T128 |
1 |
| others[1] |
232 |
1 |
|
T117 |
1 |
|
T314 |
1 |
|
T82 |
8 |
| others[2] |
245 |
1 |
|
T53 |
1 |
|
T300 |
1 |
|
T312 |
1 |
| others[3] |
453 |
1 |
|
T54 |
1 |
|
T311 |
1 |
|
T1 |
1 |
| false |
130 |
1 |
|
T184 |
1 |
|
T118 |
1 |
|
T82 |
5 |
| true |
3242 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T116 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9876 |
1 |
|
T52 |
1 |
|
T120 |
1 |
|
T247 |
1 |
| others[1] |
732 |
1 |
|
T125 |
1 |
|
T126 |
1 |
|
T1 |
1 |
| others[2] |
805 |
1 |
|
T53 |
1 |
|
T116 |
1 |
|
T311 |
1 |
| others[3] |
1292 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T184 |
1 |
| false |
405 |
1 |
|
T117 |
1 |
|
T300 |
1 |
|
T7 |
1 |
| true |
490 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9812 |
1 |
|
T45 |
1 |
|
T116 |
1 |
|
T118 |
1 |
| others[1] |
847 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T311 |
1 |
| others[2] |
776 |
1 |
|
T120 |
1 |
|
T122 |
1 |
|
T247 |
1 |
| others[3] |
1252 |
1 |
|
T125 |
1 |
|
T184 |
1 |
|
T248 |
1 |
| false |
410 |
1 |
|
T52 |
1 |
|
T117 |
1 |
|
T246 |
1 |
| true |
503 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2336 |
1 |
|
T184 |
1 |
|
T118 |
1 |
|
T120 |
1 |
| others[1] |
2280 |
1 |
|
T53 |
1 |
|
T347 |
1 |
|
T6 |
21 |
| others[2] |
2310 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T246 |
1 |
| others[3] |
3954 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T311 |
1 |
| false |
1236 |
1 |
|
T116 |
1 |
|
T248 |
1 |
|
T252 |
1 |
| true |
1484 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9335 |
1 |
|
T126 |
1 |
|
T314 |
1 |
|
T1 |
1 |
| others[1] |
274 |
1 |
|
T53 |
1 |
|
T117 |
1 |
|
T20 |
1 |
| others[2] |
278 |
1 |
|
T45 |
1 |
|
T118 |
1 |
|
T22 |
1 |
| others[3] |
430 |
1 |
|
T311 |
1 |
|
T252 |
1 |
|
T343 |
1 |
| false |
134 |
1 |
|
T127 |
1 |
|
T82 |
5 |
|
T28 |
1 |
| true |
3149 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T125 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9529 |
1 |
|
T247 |
1 |
|
T1 |
1 |
|
T6 |
100 |
| others[1] |
451 |
1 |
|
T117 |
1 |
|
T118 |
1 |
|
T122 |
1 |
| others[2] |
495 |
1 |
|
T125 |
1 |
|
T120 |
1 |
|
T248 |
1 |
| others[3] |
787 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T311 |
1 |
| false |
235 |
1 |
|
T116 |
1 |
|
T343 |
1 |
|
T350 |
1 |
| true |
2103 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9321 |
1 |
|
T248 |
1 |
|
T312 |
1 |
|
T350 |
1 |
| others[1] |
270 |
1 |
|
T124 |
1 |
|
T313 |
1 |
|
T100 |
1 |
| others[2] |
263 |
1 |
|
T45 |
1 |
|
T311 |
1 |
|
T118 |
1 |
| others[3] |
419 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T347 |
1 |
| false |
137 |
1 |
|
T122 |
1 |
|
T7 |
1 |
|
T82 |
4 |
| true |
3190 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9327 |
1 |
|
T343 |
1 |
|
T350 |
1 |
|
T6 |
100 |
| others[1] |
260 |
1 |
|
T117 |
1 |
|
T248 |
1 |
|
T124 |
1 |
| others[2] |
257 |
1 |
|
T54 |
1 |
|
T82 |
14 |
|
T73 |
1 |
| others[3] |
436 |
1 |
|
T184 |
1 |
|
T118 |
1 |
|
T246 |
1 |
| false |
136 |
1 |
|
T52 |
1 |
|
T2 |
1 |
|
T82 |
7 |
| true |
3184 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T125 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9859 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T127 |
1 |
| others[1] |
806 |
1 |
|
T118 |
1 |
|
T246 |
1 |
|
T248 |
1 |
| others[2] |
777 |
1 |
|
T53 |
1 |
|
T117 |
1 |
|
T120 |
1 |
| others[3] |
1262 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T116 |
1 |
| false |
409 |
1 |
|
T54 |
1 |
|
T300 |
1 |
|
T312 |
1 |
| true |
487 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9812 |
1 |
|
T53 |
1 |
|
T311 |
1 |
|
T118 |
1 |
| others[1] |
768 |
1 |
|
T52 |
1 |
|
T247 |
1 |
|
T314 |
1 |
| others[2] |
765 |
1 |
|
T54 |
1 |
|
T125 |
1 |
|
T184 |
1 |
| others[3] |
1322 |
1 |
|
T45 |
1 |
|
T116 |
1 |
|
T117 |
1 |
| false |
423 |
1 |
|
T248 |
1 |
|
T1 |
1 |
|
T25 |
1 |
| true |
510 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2325 |
1 |
|
T252 |
1 |
|
T124 |
1 |
|
T312 |
1 |
| others[1] |
2377 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T116 |
1 |
| others[2] |
2258 |
1 |
|
T118 |
1 |
|
T300 |
1 |
|
T127 |
1 |
| others[3] |
3907 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| false |
1214 |
1 |
|
T53 |
1 |
|
T120 |
1 |
|
T246 |
1 |
| true |
1519 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9323 |
1 |
|
T118 |
1 |
|
T300 |
1 |
|
T6 |
100 |
| others[1] |
250 |
1 |
|
T125 |
1 |
|
T116 |
1 |
|
T247 |
1 |
| others[2] |
285 |
1 |
|
T184 |
1 |
|
T124 |
1 |
|
T128 |
1 |
| others[3] |
435 |
1 |
|
T122 |
1 |
|
T127 |
1 |
|
T1 |
1 |
| false |
136 |
1 |
|
T82 |
9 |
|
T107 |
1 |
|
T88 |
2 |
| true |
3171 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |