Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9504 |
1 |
|
T184 |
1 |
|
T126 |
1 |
|
T350 |
1 |
| others[1] |
454 |
1 |
|
T54 |
1 |
|
T125 |
1 |
|
T311 |
1 |
| others[2] |
468 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T117 |
1 |
| others[3] |
729 |
1 |
|
T53 |
1 |
|
T252 |
1 |
|
T124 |
1 |
| false |
249 |
1 |
|
T82 |
5 |
|
T172 |
5 |
|
T35 |
2 |
| true |
2196 |
1 |
|
T116 |
1 |
|
T118 |
1 |
|
T122 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9318 |
1 |
|
T247 |
1 |
|
T312 |
1 |
|
T6 |
100 |
| others[1] |
245 |
1 |
|
T126 |
1 |
|
T82 |
13 |
|
T214 |
1 |
| others[2] |
247 |
1 |
|
T125 |
1 |
|
T124 |
1 |
|
T22 |
1 |
| others[3] |
458 |
1 |
|
T252 |
1 |
|
T347 |
1 |
|
T82 |
19 |
| false |
123 |
1 |
|
T53 |
1 |
|
T127 |
1 |
|
T7 |
1 |
| true |
3209 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9307 |
1 |
|
T117 |
1 |
|
T127 |
1 |
|
T6 |
100 |
| others[1] |
247 |
1 |
|
T82 |
10 |
|
T235 |
1 |
|
T28 |
1 |
| others[2] |
252 |
1 |
|
T116 |
1 |
|
T311 |
1 |
|
T120 |
1 |
| others[3] |
424 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| false |
146 |
1 |
|
T122 |
1 |
|
T252 |
1 |
|
T124 |
1 |
| true |
3224 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9817 |
1 |
|
T118 |
1 |
|
T122 |
1 |
|
T312 |
1 |
| others[1] |
759 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T248 |
1 |
| others[2] |
781 |
1 |
|
T120 |
1 |
|
T252 |
1 |
|
T350 |
1 |
| others[3] |
1362 |
1 |
|
T54 |
1 |
|
T184 |
1 |
|
T116 |
1 |
| false |
392 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T246 |
1 |
| true |
489 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9856 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T125 |
1 |
| others[1] |
793 |
1 |
|
T311 |
1 |
|
T118 |
1 |
|
T124 |
1 |
| others[2] |
805 |
1 |
|
T53 |
1 |
|
T1 |
1 |
|
T42 |
1 |
| others[3] |
1288 |
1 |
|
T116 |
1 |
|
T117 |
1 |
|
T120 |
1 |
| false |
358 |
1 |
|
T54 |
1 |
|
T21 |
1 |
|
T25 |
1 |
| true |
500 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2352 |
1 |
|
T53 |
1 |
|
T120 |
1 |
|
T248 |
1 |
| others[1] |
2419 |
1 |
|
T125 |
1 |
|
T311 |
1 |
|
T126 |
1 |
| others[2] |
2281 |
1 |
|
T54 |
1 |
|
T184 |
1 |
|
T117 |
1 |
| others[3] |
3757 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T116 |
1 |
| false |
1240 |
1 |
|
T1 |
1 |
|
T6 |
11 |
|
T25 |
1 |
| true |
1551 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9343 |
1 |
|
T52 |
1 |
|
T6 |
100 |
|
T21 |
1 |
| others[1] |
249 |
1 |
|
T45 |
1 |
|
T125 |
1 |
|
T118 |
1 |
| others[2] |
300 |
1 |
|
T54 |
1 |
|
T124 |
1 |
|
T128 |
1 |
| others[3] |
450 |
1 |
|
T184 |
1 |
|
T117 |
1 |
|
T312 |
1 |
| false |
120 |
1 |
|
T248 |
1 |
|
T20 |
1 |
|
T82 |
4 |
| true |
3138 |
1 |
|
T53 |
1 |
|
T116 |
1 |
|
T311 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9516 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| others[1] |
496 |
1 |
|
T247 |
1 |
|
T313 |
1 |
|
T22 |
1 |
| others[2] |
413 |
1 |
|
T314 |
1 |
|
T4 |
1 |
|
T12 |
1 |
| others[3] |
803 |
1 |
|
T53 |
1 |
|
T311 |
1 |
|
T118 |
1 |
| false |
212 |
1 |
|
T117 |
1 |
|
T82 |
4 |
|
T172 |
2 |
| true |
2160 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T116 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9315 |
1 |
|
T6 |
100 |
|
T30 |
62 |
|
T42 |
1 |
| others[1] |
236 |
1 |
|
T127 |
1 |
|
T313 |
1 |
|
T21 |
1 |
| others[2] |
282 |
1 |
|
T184 |
1 |
|
T116 |
1 |
|
T118 |
1 |
| others[3] |
458 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
149 |
1 |
|
T311 |
1 |
|
T82 |
5 |
|
T61 |
1 |
| true |
3160 |
1 |
|
T45 |
1 |
|
T117 |
1 |
|
T120 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9333 |
1 |
|
T45 |
1 |
|
T1 |
1 |
|
T6 |
100 |
| others[1] |
251 |
1 |
|
T122 |
1 |
|
T126 |
1 |
|
T82 |
11 |
| others[2] |
270 |
1 |
|
T300 |
1 |
|
T127 |
1 |
|
T128 |
1 |
| others[3] |
402 |
1 |
|
T125 |
1 |
|
T118 |
1 |
|
T248 |
1 |
| false |
123 |
1 |
|
T52 |
1 |
|
T312 |
1 |
|
T343 |
1 |
| true |
3221 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9822 |
1 |
|
T128 |
1 |
|
T1 |
1 |
|
T6 |
100 |
| others[1] |
810 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T116 |
1 |
| others[2] |
750 |
1 |
|
T54 |
1 |
|
T184 |
1 |
|
T117 |
1 |
| others[3] |
1361 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T118 |
1 |
| false |
374 |
1 |
|
T311 |
1 |
|
T120 |
1 |
|
T252 |
1 |
| true |
483 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9842 |
1 |
|
T120 |
1 |
|
T122 |
1 |
|
T6 |
100 |
| others[1] |
767 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T184 |
1 |
| others[2] |
798 |
1 |
|
T117 |
1 |
|
T252 |
1 |
|
T300 |
1 |
| others[3] |
1283 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T125 |
1 |
| false |
392 |
1 |
|
T246 |
1 |
|
T82 |
11 |
|
T172 |
9 |
| true |
518 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T22 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2286 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T122 |
1 |
| others[1] |
2317 |
1 |
|
T184 |
1 |
|
T117 |
1 |
|
T120 |
1 |
| others[2] |
2448 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T311 |
1 |
| others[3] |
3852 |
1 |
|
T116 |
1 |
|
T118 |
1 |
|
T246 |
1 |
| false |
1171 |
1 |
|
T125 |
1 |
|
T300 |
1 |
|
T350 |
1 |
| true |
1526 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9347 |
1 |
|
T252 |
1 |
|
T128 |
1 |
|
T6 |
100 |
| others[1] |
287 |
1 |
|
T126 |
1 |
|
T26 |
1 |
|
T99 |
1 |
| others[2] |
279 |
1 |
|
T116 |
1 |
|
T120 |
1 |
|
T122 |
1 |
| others[3] |
439 |
1 |
|
T246 |
1 |
|
T300 |
1 |
|
T312 |
1 |
| false |
138 |
1 |
|
T54 |
1 |
|
T343 |
1 |
|
T82 |
4 |
| true |
3110 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9519 |
1 |
|
T247 |
1 |
|
T4 |
1 |
|
T6 |
100 |
| others[1] |
430 |
1 |
|
T124 |
1 |
|
T1 |
1 |
|
T99 |
1 |
| others[2] |
447 |
1 |
|
T54 |
1 |
|
T118 |
1 |
|
T20 |
1 |
| others[3] |
740 |
1 |
|
T52 |
1 |
|
T117 |
1 |
|
T120 |
1 |
| false |
247 |
1 |
|
T125 |
1 |
|
T248 |
1 |
|
T82 |
5 |
| true |
2217 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9325 |
1 |
|
T124 |
1 |
|
T127 |
1 |
|
T6 |
100 |
| others[1] |
238 |
1 |
|
T122 |
1 |
|
T128 |
1 |
|
T82 |
12 |
| others[2] |
254 |
1 |
|
T300 |
1 |
|
T26 |
1 |
|
T82 |
6 |
| others[3] |
453 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T116 |
1 |
| false |
148 |
1 |
|
T20 |
1 |
|
T23 |
1 |
|
T82 |
4 |
| true |
3182 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T125 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9296 |
1 |
|
T247 |
1 |
|
T6 |
100 |
|
T7 |
1 |
| others[1] |
273 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T184 |
1 |
| others[2] |
260 |
1 |
|
T126 |
1 |
|
T343 |
1 |
|
T128 |
1 |
| others[3] |
407 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T116 |
1 |
| false |
153 |
1 |
|
T312 |
1 |
|
T100 |
1 |
|
T82 |
2 |
| true |
3211 |
1 |
|
T45 |
1 |
|
T311 |
1 |
|
T117 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9841 |
1 |
|
T45 |
1 |
|
T184 |
1 |
|
T120 |
1 |
| others[1] |
755 |
1 |
|
T117 |
1 |
|
T12 |
1 |
|
T82 |
20 |
| others[2] |
803 |
1 |
|
T116 |
1 |
|
T122 |
1 |
|
T124 |
1 |
| others[3] |
1285 |
1 |
|
T52 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| false |
418 |
1 |
|
T25 |
1 |
|
T82 |
9 |
|
T172 |
8 |
| true |
498 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9841 |
1 |
|
T116 |
1 |
|
T311 |
1 |
|
T117 |
1 |
| others[1] |
776 |
1 |
|
T45 |
1 |
|
T343 |
1 |
|
T1 |
1 |
| others[2] |
758 |
1 |
|
T53 |
1 |
|
T118 |
1 |
|
T120 |
1 |
| others[3] |
1308 |
1 |
|
T125 |
1 |
|
T184 |
1 |
|
T247 |
1 |
| false |
401 |
1 |
|
T52 |
1 |
|
T54 |
1 |
|
T300 |
1 |
| true |
516 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2325 |
1 |
|
T247 |
1 |
|
T127 |
1 |
|
T314 |
1 |
| others[1] |
2329 |
1 |
|
T116 |
1 |
|
T126 |
1 |
|
T343 |
1 |
| others[2] |
2354 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T184 |
1 |
| others[3] |
3900 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T54 |
1 |
| false |
1180 |
1 |
|
T300 |
1 |
|
T1 |
1 |
|
T6 |
11 |
| true |
1512 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T34 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9338 |
1 |
|
T6 |
100 |
|
T26 |
1 |
|
T30 |
62 |
| others[1] |
286 |
1 |
|
T247 |
1 |
|
T82 |
17 |
|
T214 |
1 |
| others[2] |
283 |
1 |
|
T118 |
1 |
|
T126 |
1 |
|
T313 |
1 |
| others[3] |
421 |
1 |
|
T246 |
1 |
|
T248 |
1 |
|
T312 |
1 |
| false |
131 |
1 |
|
T52 |
1 |
|
T125 |
1 |
|
T82 |
4 |
| true |
3141 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9505 |
1 |
|
T54 |
1 |
|
T116 |
1 |
|
T247 |
1 |
| others[1] |
473 |
1 |
|
T45 |
1 |
|
T246 |
1 |
|
T124 |
1 |
| others[2] |
459 |
1 |
|
T314 |
1 |
|
T34 |
1 |
|
T82 |
7 |
| others[3] |
781 |
1 |
|
T117 |
1 |
|
T120 |
1 |
|
T122 |
1 |
| false |
243 |
1 |
|
T52 |
1 |
|
T126 |
1 |
|
T313 |
1 |
| true |
2139 |
1 |
|
T53 |
1 |
|
T125 |
1 |
|
T184 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9326 |
1 |
|
T116 |
1 |
|
T6 |
100 |
|
T22 |
1 |
| others[1] |
224 |
1 |
|
T120 |
1 |
|
T127 |
1 |
|
T347 |
1 |
| others[2] |
237 |
1 |
|
T246 |
1 |
|
T252 |
1 |
|
T312 |
1 |
| others[3] |
463 |
1 |
|
T117 |
1 |
|
T118 |
1 |
|
T313 |
1 |
| false |
131 |
1 |
|
T23 |
1 |
|
T82 |
3 |
|
T27 |
1 |
| true |
3219 |
1 |
|
T45 |
1 |
|
T52 |
1 |
|
T53 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9295 |
1 |
|
T313 |
1 |
|
T6 |
100 |
|
T30 |
62 |
| others[1] |
247 |
1 |
|
T125 |
1 |
|
T120 |
1 |
|
T246 |
1 |
| others[2] |
270 |
1 |
|
T118 |
1 |
|
T128 |
1 |
|
T1 |
1 |
| others[3] |
454 |
1 |
|
T52 |
1 |
|
T248 |
1 |
|
T252 |
1 |
| false |
147 |
1 |
|
T116 |
1 |
|
T343 |
1 |
|
T350 |
1 |
| true |
3187 |
1 |
|
T45 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9823 |
1 |
|
T53 |
1 |
|
T247 |
1 |
|
T248 |
1 |
| others[1] |
784 |
1 |
|
T52 |
1 |
|
T184 |
1 |
|
T120 |
1 |
| others[2] |
826 |
1 |
|
T122 |
1 |
|
T252 |
1 |
|
T300 |
1 |
| others[3] |
1256 |
1 |
|
T45 |
1 |
|
T54 |
1 |
|
T118 |
1 |
| false |
412 |
1 |
|
T125 |
1 |
|
T116 |
1 |
|
T311 |
1 |
| true |
499 |
1 |
|
T4 |
1 |
|
T20 |
1 |
|
T22 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |