Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	222937	1		T2	499		T4	499		T5	402
auto[FlashEraseBank]	254342	1		T2	393		T4	435		T20	1

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	263578	1		T2	892		T4	934		T5	10
auto[FlashOpProgram]	194548	1		T5	384		T12	26		T6	100
auto[FlashOpErase]	15153	1		T5	8		T12	10		T6	100
auto[FlashOpInvalid]	4000	1		T6	200		T87	200		T104	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	263578	1		T2	892		T4	934		T5	10
op[FlashOpProgram]	194548	1		T5	384		T12	26		T6	100
op[FlashOpErase]	15153	1		T5	8		T12	10		T6	100
read_erase_read	713	1		T5	2		T8	2		T82	10
read_prog_read	1276	1		T12	4		T22	4		T34	29

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	339665	1		T2	892		T4	823		T20	2
auto[FlashPartInfo]	133792	1		T4	71		T5	402		T12	1
auto[FlashPartInfo1]	818	1		T4	15		T26	2		T42	3
auto[FlashPartInfo2]	3004	1		T4	25		T6	6		T21	2

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	201382	1		T2	892		T4	823		T20	2
auto[FlashPartData]	auto[FlashOpProgram]	130564	1		T12	26		T6	97		T21	1104
auto[FlashPartData]	auto[FlashOpErase]	3803	1		T12	10		T6	97		T25	2
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T6	194		T87	196		T104	196
auto[FlashPartInfo]	auto[FlashOpRead]	59779	1		T4	71		T5	10		T12	1
auto[FlashPartInfo]	auto[FlashOpProgram]	62644	1		T5	384		T6	2		T21	176
auto[FlashPartInfo]	auto[FlashOpErase]	11307	1		T5	8		T6	2		T8	8
auto[FlashPartInfo]	auto[FlashOpInvalid]	62	1		T6	4		T87	2		T104	2
auto[FlashPartInfo1]	auto[FlashOpRead]	645	1		T4	15		T26	2		T42	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T105	32		T95	1		T381	32
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T88	1		T95	1		T382	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T95	2		T382	2		T383	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1772	1		T4	25		T6	2		T22	5
auto[FlashPartInfo2]	auto[FlashOpProgram]	1177	1		T6	1		T21	2		T22	2
auto[FlashPartInfo2]	auto[FlashOpErase]	39	1		T6	1		T82	1		T87	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	16	1		T6	2		T87	2		T104	2