Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29119	1		T6	400		T82	32		T24	32
auto[1]	90	1		T177	4		T384	1		T385	2
auto[2]	322	1		T34	39		T203	2		T269	40
auto[3]	303	1		T57	1		T214	25		T205	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7510	1		T6	100		T34	9		T82	8
evic_idx[1]	7469	1		T6	100		T34	7		T82	8
evic_idx[2]	7436	1		T6	100		T34	13		T82	8
evic_idx[3]	7419	1		T6	100		T34	10		T82	8

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28617	1		T6	400		T24	16		T85	4
evic_op[2]	533	1		T34	39		T82	4		T24	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7044	1		T6	100		T24	4		T85	1
evic_idx[0]	evic_op[1]	auto[1]	39	1		T386	39		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	32	1		T351	10		T387	22		-	-
evic_idx[0]	evic_op[1]	auto[3]	91	1		T214	4		T388	8		T389	4
evic_idx[0]	evic_op[2]	auto[0]	80	1		T82	1		T24	4		T35	1
evic_idx[0]	evic_op[2]	auto[1]	1	1		T177	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	44	1		T34	9		T203	2		T269	9
evic_idx[0]	evic_op[2]	auto[3]	8	1		T390	1		T391	1		T392	1
evic_idx[1]	evic_op[1]	auto[0]	7046	1		T6	100		T24	4		T85	1
evic_idx[1]	evic_op[1]	auto[1]	19	1		T386	19		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	22	1		T351	5		T387	17		-	-
evic_idx[1]	evic_op[1]	auto[3]	66	1		T214	10		T388	7		T393	10
evic_idx[1]	evic_op[2]	auto[0]	74	1		T82	1		T24	4		T271	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T177	1		T384	1		T385	1
evic_idx[1]	evic_op[2]	auto[2]	55	1		T34	7		T269	13		T107	2
evic_idx[1]	evic_op[2]	auto[3]	12	1		T57	1		T106	1		T390	1
evic_idx[2]	evic_op[1]	auto[0]	7046	1		T6	100		T24	4		T85	1
evic_idx[2]	evic_op[1]	auto[1]	12	1		T386	12		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	18	1		T351	9		T387	9		-	-
evic_idx[2]	evic_op[1]	auto[3]	55	1		T214	5		T388	9		T389	1
evic_idx[2]	evic_op[2]	auto[0]	75	1		T82	1		T24	4		T68	1
evic_idx[2]	evic_op[2]	auto[1]	4	1		T177	1		T385	1		T394	2
evic_idx[2]	evic_op[2]	auto[2]	46	1		T34	13		T269	8		T107	4
evic_idx[2]	evic_op[2]	auto[3]	9	1		T205	1		T391	1		T395	1
evic_idx[3]	evic_op[1]	auto[0]	7048	1		T6	100		T24	4		T85	1
evic_idx[3]	evic_op[1]	auto[1]	9	1		T386	9		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	18	1		T351	8		T387	10		-	-
evic_idx[3]	evic_op[1]	auto[3]	52	1		T214	6		T388	7		T393	7
evic_idx[3]	evic_op[2]	auto[0]	66	1		T82	1		T24	4		T272	5
evic_idx[3]	evic_op[2]	auto[1]	2	1		T177	1		T394	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	43	1		T34	10		T269	10		T107	2
evic_idx[3]	evic_op[2]	auto[3]	10	1		T205	1		T395	1		T396	1