Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	48819	1		T58	2705		T59	1552		T60	5149
prog_lvl[2]	1019	1		T58	29		T59	775		T397	147
prog_lvl[3]	1	1		T59	1		-	-		-	-

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	7352	1		T4	299		T61	11		T344	48
rd_lvl[2]	8188	1		T4	703		T61	429		T344	102
rd_lvl[3]	11928	1		T61	16		T344	943		T62	14
rd_lvl[4]	16102	1		T61	13		T344	617		T62	5
rd_lvl[5]	10315	1		T4	32		T61	6		T62	7
rd_lvl[6]	13611	1		T2	862		T61	382		T62	508
rd_lvl[7]	19145	1		T2	922		T61	1306		T344	84
rd_lvl[8]	11637	1		T61	595		T398	1459		T399	634
rd_lvl[9]	4090	1		T61	2		T398	421		T222	7
rd_lvl[10]	3892	1		T62	493		T224	33		T400	21
rd_lvl[11]	4231	1		T7	471		T61	63		T62	434
rd_lvl[12]	5030	1		T7	316		T63	431		T401	638
rd_lvl[13]	5540	1		T402	198		T403	712		T401	190
rd_lvl[14]	5361	1		T62	59		T402	617		T278	826
rd_lvl[15]	3419	1		T63	3		T278	358		T404	191