Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	314380	1		T45	1		T52	5		T53	5
all_pins[1]	314380	1		T45	1		T52	5		T53	5
all_pins[2]	314380	1		T45	1		T52	5		T53	5
all_pins[3]	314380	1		T45	1		T52	5		T53	5
all_pins[4]	314380	1		T45	1		T52	5		T53	5
all_pins[5]	314380	1		T45	1		T52	5		T53	5

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1531842	1		T45	6		T52	22		T53	25
values[0x1]	354438	1		T52	8		T53	5		T54	11
transitions[0x0=>0x1]	337837	1		T52	4		T53	4		T54	5
transitions[0x1=>0x0]	337846	1		T52	4		T53	5		T54	5

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	250536	1		T45	1		T52	5		T53	5
all_pins[0]	values[0x1]	63844	1		T54	1		T125	2		T311	2
all_pins[0]	transitions[0x0=>0x1]	63824	1		T54	1		T125	2		T311	2
all_pins[0]	transitions[0x1=>0x0]	54478	1		T52	1		T53	2		T54	2
all_pins[1]	values[0x0]	259882	1		T45	1		T52	4		T53	3
all_pins[1]	values[0x1]	54498	1		T52	1		T53	2		T54	2
all_pins[1]	transitions[0x0=>0x1]	54481	1		T52	1		T53	2		T125	2
all_pins[1]	transitions[0x1=>0x0]	7487	1		T52	2		T125	2		T184	4
all_pins[2]	values[0x0]	306876	1		T45	1		T52	3		T53	5
all_pins[2]	values[0x1]	7504	1		T52	2		T54	2		T125	2
all_pins[2]	transitions[0x0=>0x1]	5824	1		T54	2		T125	2		T184	2
all_pins[2]	transitions[0x1=>0x0]	130572	1		T54	1		T246	1		T248	1
all_pins[3]	values[0x0]	182128	1		T45	1		T52	3		T53	5
all_pins[3]	values[0x1]	132252	1		T52	2		T54	1		T184	2
all_pins[3]	transitions[0x0=>0x1]	117406	1		T184	1		T246	1		T247	1
all_pins[3]	transitions[0x1=>0x0]	81428	1		T52	1		T54	2		T184	2
all_pins[4]	values[0x0]	218106	1		T45	1		T52	2		T53	5
all_pins[4]	values[0x1]	96274	1		T52	3		T54	3		T184	3
all_pins[4]	transitions[0x0=>0x1]	96257	1		T52	3		T54	1		T184	3
all_pins[4]	transitions[0x1=>0x0]	49	1		T53	3		T246	1		T248	1
all_pins[5]	values[0x0]	314314	1		T45	1		T52	5		T53	2
all_pins[5]	values[0x1]	66	1		T53	3		T54	2		T246	4
all_pins[5]	transitions[0x0=>0x1]	45	1		T53	2		T54	1		T246	3
all_pins[5]	transitions[0x1=>0x0]	63832	1		T125	2		T311	2		T252	3