Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	254	1		T52	4		T53	4		T54	4
all_values[1]	254	1		T52	4		T53	4		T54	4
all_values[2]	254	1		T52	4		T53	4		T54	4
all_values[3]	254	1		T52	4		T53	4		T54	4
all_values[4]	254	1		T52	4		T53	4		T54	4
all_values[5]	254	1		T52	4		T53	4		T54	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	839	1		T52	15		T53	11		T54	13
auto[1]	685	1		T52	9		T53	13		T54	11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	575	1		T52	11		T53	7		T54	9
auto[1]	949	1		T52	13		T53	17		T54	15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	905	1		T52	14		T53	13		T54	16
auto[1]	619	1		T52	10		T53	11		T54	8

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	61	1		T52	1		T54	1		T125	1
all_values[0]	auto[0]	auto[0]	auto[1]	24	1		T53	1		T184	1		T311	1
all_values[0]	auto[0]	auto[1]	auto[0]	34	1		T52	2		T53	1		T54	1
all_values[0]	auto[0]	auto[1]	auto[1]	28	1		T125	1		T311	1		T252	1
all_values[0]	auto[1]	auto[0]	auto[1]	45	1		T52	1		T125	2		T311	1
all_values[0]	auto[1]	auto[1]	auto[1]	62	1		T53	2		T54	2		T184	1
all_values[1]	auto[0]	auto[0]	auto[0]	64	1		T52	3		T54	1		T184	2
all_values[1]	auto[0]	auto[0]	auto[1]	21	1		T248	1		T312	1		T313	1
all_values[1]	auto[0]	auto[1]	auto[0]	32	1		T53	1		T54	1		T125	1
all_values[1]	auto[0]	auto[1]	auto[1]	32	1		T53	1		T54	1		T311	1
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T52	1		T54	1		T125	1
all_values[1]	auto[1]	auto[1]	auto[1]	39	1		T53	2		T125	2		T184	1
all_values[2]	auto[0]	auto[0]	auto[0]	63	1		T52	1		T53	2		T54	1
all_values[2]	auto[0]	auto[0]	auto[1]	22	1		T54	1		T125	1		T311	1
all_values[2]	auto[0]	auto[1]	auto[0]	34	1		T53	1		T246	2		T314	4
all_values[2]	auto[0]	auto[1]	auto[1]	36	1		T52	1		T54	1		T125	1
all_values[2]	auto[1]	auto[0]	auto[1]	67	1		T52	1		T53	1		T54	1
all_values[2]	auto[1]	auto[1]	auto[1]	32	1		T52	1		T247	1		T248	1
all_values[3]	auto[0]	auto[0]	auto[0]	51	1		T53	1		T54	2		T125	1
all_values[3]	auto[0]	auto[0]	auto[1]	26	1		T53	1		T184	1		T311	2
all_values[3]	auto[0]	auto[1]	auto[0]	42	1		T125	1		T246	1		T248	2
all_values[3]	auto[0]	auto[1]	auto[1]	25	1		T52	1		T54	1		T184	1
all_values[3]	auto[1]	auto[0]	auto[1]	59	1		T52	2		T53	2		T54	1
all_values[3]	auto[1]	auto[1]	auto[1]	51	1		T52	1		T184	1		T246	1
all_values[4]	auto[0]	auto[0]	auto[0]	53	1		T125	1		T247	1		T248	3
all_values[4]	auto[0]	auto[0]	auto[1]	28	1		T53	1		T246	1		T247	1
all_values[4]	auto[0]	auto[1]	auto[0]	44	1		T53	1		T125	1		T311	1
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T52	1		T54	2		T184	2
all_values[4]	auto[1]	auto[0]	auto[1]	52	1		T52	2		T54	2		T184	2
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T52	1		T53	2		T125	2
all_values[5]	auto[0]	auto[0]	auto[0]	55	1		T52	3		T54	1		T125	3
all_values[5]	auto[0]	auto[0]	auto[1]	28	1		T53	1		T311	2		T247	1
all_values[5]	auto[0]	auto[1]	auto[0]	42	1		T52	1		T54	1		T184	1
all_values[5]	auto[0]	auto[1]	auto[1]	30	1		T53	1		T54	1		T246	2
all_values[5]	auto[1]	auto[0]	auto[1]	54	1		T53	1		T54	1		T184	2
all_values[5]	auto[1]	auto[1]	auto[1]	45	1		T53	1		T125	1		T246	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal