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 LINE       11942
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T15,T44,T45
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T47,T52

 LINE       11942
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T45,T46,T47
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T45,T47,T49
1	1	Covered	T45,T47,T53

 LINE       11942
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T45,T47,T52
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T45,T46,T47
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T47,T49

 LINE       11942
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[28] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[29] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[30] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[31] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[32] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[33] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[34] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[35] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[36] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[37] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[38] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[39] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[40] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[41] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T53

 LINE       11942
 SUB-EXPRESSION (addr_hit[42] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[43] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T47,T48

 LINE       11942
 SUB-EXPRESSION (addr_hit[44] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[45] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[46] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T47,T53

 LINE       11942
 SUB-EXPRESSION (addr_hit[47] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[48] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[49] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[50] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[51] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[52] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[53] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[54] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[55] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[56] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[57] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[58] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[59] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T47,T49

 LINE       11942
 SUB-EXPRESSION (addr_hit[60] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[61] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[62] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[63] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[64] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[65] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T47,T48

 LINE       11942
 SUB-EXPRESSION (addr_hit[66] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[67] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[68] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[69] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T47,T53

 LINE       11942
 SUB-EXPRESSION (addr_hit[70] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[71] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[72] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[73] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[74] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[75] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[76] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[77] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[78] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[79] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[80] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[81] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[82] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[83] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[84] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[85] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[86] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[87] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[88] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[89] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[90] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[91] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[92] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T47,T49

 LINE       11942
 SUB-EXPRESSION (addr_hit[93] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T15,T44,T45
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[94] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[95] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[96] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[97] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[98] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[99] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[100] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[101] & ((|(4'b0111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[102] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T45,T46,T47
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[103] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[104] & ((|(4'b1111 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[105] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       11942
 SUB-EXPRESSION (addr_hit[106] & ((|(4'b1 & (~reg_be)))))
                 ------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T44,T45,T46
1	0	Covered	T44,T45,T46
1	1	Covered	T45,T46,T47

 LINE       11942
 SUB-EXPRESSION (addr_hit[107] & ((|(4'b0011 & (~reg_be)))))
                 ------1------   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T44,T45
1	0	Covered	T44,T45,T46
1	1	Covered	T44,T45,T46

 LINE       12054
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T15,T44,T45
1	1	0	Covered	T116,T122,T127
1	1	1	Covered	T52,T53,T54

 LINE       12067
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T127
1	1	1	Covered	T44,T46,T47

 LINE       12080
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T45,T46,T47
1	1	0	Covered	T116,T118,T127
1	1	1	Covered	T52,T53,T54

 LINE       12093
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T128,T258
1	1	1	Covered	T44,T46,T47

 LINE       12104
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T45,T47,T53
1	1	0	Covered	T126,T127,T259
1	1	1	Covered	T13,T133,T156

 LINE       12107
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T126,T128
1	1	1	Covered	T44,T46,T47

 LINE       12110
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T45,T46,T47
1	1	0	Covered	T45,T122,T126
1	1	1	Covered	T45,T52,T53

 LINE       12113
 EXPRESSION (addr_hit[7] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T44,T45
1	0	1	Covered	T44,T45,T46
1	1	0	Not Covered
1	1	1	Covered	T50,T119,T121

 LINE       12114
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T127
1	1	1	Covered	T44,T46,T47

 LINE       12129
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T126
1	1	1	Covered	T44,T46,T47

 LINE       12132
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T260
1	1	1	Covered	T44,T46,T47

 LINE       12137
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T45,T46,T47
1	1	0	Covered	T116,T127,T128
1	1	1	Covered	T30,T138,T135

 LINE       12140
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T49,T126,T127
1	1	1	Covered	T44,T46,T47

 LINE       12143
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T122
1	1	1	Covered	T44,T46,T47

 LINE       12146
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T118,T127
1	1	1	Covered	T44,T46,T47

 LINE       12149
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T118
1	1	1	Covered	T44,T46,T47

 LINE       12152
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T118,T122
1	1	1	Covered	T44,T46,T47

 LINE       12155
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T122,T126
1	1	1	Covered	T44,T46,T47

 LINE       12158
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T260
1	1	1	Covered	T44,T46,T47

 LINE       12161
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T127,T128
1	1	1	Covered	T44,T46,T47

 LINE       12164
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T261,T260
1	1	1	Covered	T44,T45,T46

 LINE       12179
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T127,T128,T239
1	1	1	Covered	T44,T45,T46

 LINE       12194
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T126
1	1	1	Covered	T44,T45,T46

 LINE       12209
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T56
1	1	1	Covered	T44,T45,T46

 LINE       12224
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T238,T261
1	1	1	Covered	T44,T45,T46