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 LINE       12239
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T126
1	1	1	Covered	T44,T45,T46

 LINE       12254
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T128
1	1	1	Covered	T44,T45,T46

 LINE       12269
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12284
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T128,T239
1	1	1	Covered	T44,T45,T46

 LINE       12289
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T118,T122,T126
1	1	1	Covered	T44,T45,T46

 LINE       12294
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T239
1	1	1	Covered	T44,T45,T46

 LINE       12299
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T118,T122
1	1	1	Covered	T44,T45,T46

 LINE       12304
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T239
1	1	1	Covered	T44,T45,T46

 LINE       12309
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T239
1	1	1	Covered	T44,T45,T46

 LINE       12314
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T237,T126
1	1	1	Covered	T44,T45,T46

 LINE       12319
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T128
1	1	1	Covered	T44,T45,T46

 LINE       12324
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12337
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T127
1	1	1	Covered	T44,T46,T47

 LINE       12340
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T118,T128
1	1	1	Covered	T44,T46,T47

 LINE       12343
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T126
1	1	1	Covered	T44,T46,T47

 LINE       12346
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T128
1	1	1	Covered	T44,T46,T47

 LINE       12349
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T127,T128
1	1	1	Covered	T44,T46,T47

 LINE       12352
 EXPRESSION (addr_hit[42] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T238,T239
1	1	1	Covered	T44,T46,T47

 LINE       12355
 EXPRESSION (addr_hit[43] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T128
1	1	1	Covered	T44,T46,T47

 LINE       12358
 EXPRESSION (addr_hit[44] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T56
1	1	1	Covered	T44,T46,T47

 LINE       12361
 EXPRESSION (addr_hit[45] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T126
1	1	1	Covered	T44,T46,T47

 LINE       12364
 EXPRESSION (addr_hit[46] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T55
1	1	1	Covered	T44,T46,T47

 LINE       12367
 EXPRESSION (addr_hit[47] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12382
 EXPRESSION (addr_hit[48] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12397
 EXPRESSION (addr_hit[49] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T126
1	1	1	Covered	T44,T45,T46

 LINE       12412
 EXPRESSION (addr_hit[50] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T239,T262
1	1	1	Covered	T44,T45,T46

 LINE       12427
 EXPRESSION (addr_hit[51] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T118,T128
1	1	1	Covered	T44,T45,T46

 LINE       12442
 EXPRESSION (addr_hit[52] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12457
 EXPRESSION (addr_hit[53] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T128
1	1	1	Covered	T44,T45,T46

 LINE       12472
 EXPRESSION (addr_hit[54] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12487
 EXPRESSION (addr_hit[55] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T118,T126
1	1	1	Covered	T44,T45,T46

 LINE       12502
 EXPRESSION (addr_hit[56] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T261
1	1	1	Covered	T44,T45,T46

 LINE       12517
 EXPRESSION (addr_hit[57] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T127
1	1	1	Covered	T44,T46,T47

 LINE       12520
 EXPRESSION (addr_hit[58] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T127,T128,T260
1	1	1	Covered	T44,T45,T46

 LINE       12535
 EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T127
1	1	1	Covered	T44,T46,T47

 LINE       12538
 EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T263
1	1	1	Covered	T44,T46,T47

 LINE       12541
 EXPRESSION (addr_hit[61] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T118,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12556
 EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T126,T261
1	1	1	Covered	T44,T45,T46

 LINE       12571
 EXPRESSION (addr_hit[63] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T126,T261
1	1	1	Covered	T44,T46,T47

 LINE       12574
 EXPRESSION (addr_hit[64] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T260
1	1	1	Covered	T44,T46,T47

 LINE       12577
 EXPRESSION (addr_hit[65] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T127,T128,T264
1	1	1	Covered	T44,T46,T47

 LINE       12580
 EXPRESSION (addr_hit[66] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T128,T260
1	1	1	Covered	T44,T46,T47

 LINE       12583
 EXPRESSION (addr_hit[67] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T128
1	1	1	Covered	T44,T46,T47

 LINE       12586
 EXPRESSION (addr_hit[68] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T128
1	1	1	Covered	T44,T46,T47

 LINE       12589
 EXPRESSION (addr_hit[69] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T122
1	1	1	Covered	T44,T46,T47

 LINE       12592
 EXPRESSION (addr_hit[70] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T118,T126,T127
1	1	1	Covered	T44,T46,T47

 LINE       12595
 EXPRESSION (addr_hit[71] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T127,T128,T261
1	1	1	Covered	T44,T46,T47

 LINE       12598
 EXPRESSION (addr_hit[72] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T126,T128
1	1	1	Covered	T44,T46,T47

 LINE       12601
 EXPRESSION (addr_hit[73] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T127,T128
1	1	1	Covered	T44,T45,T46

 LINE       12616
 EXPRESSION (addr_hit[74] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T261
1	1	1	Covered	T44,T45,T46

 LINE       12631
 EXPRESSION (addr_hit[75] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T127,T261
1	1	1	Covered	T44,T45,T46

 LINE       12646
 EXPRESSION (addr_hit[76] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T127,T128
1	1	1	Covered	T44,T45,T46

 LINE       12661
 EXPRESSION (addr_hit[77] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T126
1	1	1	Covered	T44,T45,T46

 LINE       12676
 EXPRESSION (addr_hit[78] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T118,T128
1	1	1	Covered	T44,T45,T46

 LINE       12691
 EXPRESSION (addr_hit[79] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12706
 EXPRESSION (addr_hit[80] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T49,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12721
 EXPRESSION (addr_hit[81] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T126
1	1	1	Covered	T44,T45,T46

 LINE       12736
 EXPRESSION (addr_hit[82] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T128
1	1	1	Covered	T44,T45,T46

 LINE       12751
 EXPRESSION (addr_hit[83] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T128,T239
1	1	1	Covered	T44,T46,T47

 LINE       12754
 EXPRESSION (addr_hit[84] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T118,T126
1	1	1	Covered	T44,T45,T46

 LINE       12769
 EXPRESSION (addr_hit[85] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T260
1	1	1	Covered	T44,T46,T47

 LINE       12772
 EXPRESSION (addr_hit[86] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T261,T260
1	1	1	Covered	T44,T46,T47

 LINE       12775
 EXPRESSION (addr_hit[87] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12790
 EXPRESSION (addr_hit[88] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T127
1	1	1	Covered	T44,T45,T46

 LINE       12805
 EXPRESSION (addr_hit[89] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T122,T127,T239
1	1	1	Covered	T44,T46,T47

 LINE       12810
 EXPRESSION (addr_hit[90] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T116,T118
1	1	1	Covered	T44,T46,T47

 LINE       12813
 EXPRESSION (addr_hit[91] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T44,T45
1	0	1	Covered	T44,T45,T46
1	1	0	Not Covered
1	1	1	Covered	T44,T46,T47

 LINE       12814
 EXPRESSION (addr_hit[91] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T45,T122,T127
1	1	1	Covered	T44,T46,T47

 LINE       12819
 EXPRESSION (addr_hit[92] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T260,T264
1	1	1	Covered	T44,T46,T47

 LINE       12824
 EXPRESSION (addr_hit[94] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T44,T45
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T55,T265
1	1	1	Covered	T44,T46,T47

 LINE       12825
 EXPRESSION (addr_hit[95] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T126,T261
1	1	1	Covered	T44,T46,T47

 LINE       12842
 EXPRESSION (addr_hit[99] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T126,T127,T260
1	1	1	Covered	T44,T46,T47

 LINE       12847
 EXPRESSION (addr_hit[102] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T45,T46,T47
1	1	0	Covered	T126,T127,T128
1	1	1	Not Covered

 LINE       12852
 EXPRESSION (addr_hit[104] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T49,T116,T126
1	1	1	Covered	T44,T46,T47

 LINE       12855
 EXPRESSION (addr_hit[105] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T118,T122
1	1	1	Covered	T44,T46,T47

 LINE       12860
 EXPRESSION (addr_hit[106] & reg_we & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T44,T45,T46
1	0	1	Covered	T44,T45,T46
1	1	0	Covered	T116,T122,T126
1	1	1	Covered	T44,T46,T47

 LINE       12863
 EXPRESSION (addr_hit[107] & reg_re & ((!reg_error)))
             ------1------   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T15,T44,T45
1	0	1	Covered	T44,T45,T46
1	1	0	Not Covered
1	1	1	Covered	T44,T46,T47

 LINE       13724
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T15,T44,T45