| T1038 |
/workspace/coverage/default/14.flash_ctrl_rand_ops.2645990962 |
|
|
Dec 31 12:51:11 PM PST 23 |
Dec 31 01:02:51 PM PST 23 |
109229300 ps |
| T1039 |
/workspace/coverage/default/5.flash_ctrl_alert_test.2577373272 |
|
|
Dec 31 12:50:34 PM PST 23 |
Dec 31 12:51:00 PM PST 23 |
67389800 ps |
| T1040 |
/workspace/coverage/default/7.flash_ctrl_connect.2503797728 |
|
|
Dec 31 12:50:59 PM PST 23 |
Dec 31 12:51:31 PM PST 23 |
47751600 ps |
| T1041 |
/workspace/coverage/default/39.flash_ctrl_connect.19519018 |
|
|
Dec 31 12:51:33 PM PST 23 |
Dec 31 12:51:54 PM PST 23 |
24829000 ps |
| T1042 |
/workspace/coverage/default/24.flash_ctrl_rw_evict.1964835079 |
|
|
Dec 31 12:51:22 PM PST 23 |
Dec 31 12:52:01 PM PST 23 |
70985800 ps |
| T1043 |
/workspace/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3309732068 |
|
|
Dec 31 12:50:51 PM PST 23 |
Dec 31 12:54:18 PM PST 23 |
36727807200 ps |
| T1044 |
/workspace/coverage/default/1.flash_ctrl_serr_counter.962959833 |
|
|
Dec 31 12:50:22 PM PST 23 |
Dec 31 12:51:46 PM PST 23 |
3339752000 ps |
| T1045 |
/workspace/coverage/default/17.flash_ctrl_prog_reset.2064578516 |
|
|
Dec 31 12:51:12 PM PST 23 |
Dec 31 12:51:34 PM PST 23 |
18838100 ps |
| T1046 |
/workspace/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3088402514 |
|
|
Dec 31 12:51:00 PM PST 23 |
Dec 31 12:52:47 PM PST 23 |
10019895300 ps |
| T1047 |
/workspace/coverage/default/45.flash_ctrl_disable.1032077921 |
|
|
Dec 31 12:51:18 PM PST 23 |
Dec 31 12:51:48 PM PST 23 |
10539600 ps |
| T1048 |
/workspace/coverage/default/14.flash_ctrl_hw_sec_otp.1253595823 |
|
|
Dec 31 12:51:30 PM PST 23 |
Dec 31 12:53:23 PM PST 23 |
12766869500 ps |
| T1049 |
/workspace/coverage/default/10.flash_ctrl_hw_rma_reset.1950256306 |
|
|
Dec 31 12:50:39 PM PST 23 |
Dec 31 01:03:32 PM PST 23 |
40127545300 ps |
| T1050 |
/workspace/coverage/default/13.flash_ctrl_wo.4136895383 |
|
|
Dec 31 12:50:51 PM PST 23 |
Dec 31 12:53:36 PM PST 23 |
4392090600 ps |
| T1051 |
/workspace/coverage/default/15.flash_ctrl_prog_reset.2119838339 |
|
|
Dec 31 12:51:09 PM PST 23 |
Dec 31 12:51:33 PM PST 23 |
22311300 ps |
| T1052 |
/workspace/coverage/default/21.flash_ctrl_rw_evict.3493662605 |
|
|
Dec 31 12:51:35 PM PST 23 |
Dec 31 12:52:20 PM PST 23 |
164099200 ps |
| T1053 |
/workspace/coverage/default/2.flash_ctrl_error_mp.2649658110 |
|
|
Dec 31 12:50:35 PM PST 23 |
Dec 31 01:26:52 PM PST 23 |
9445522900 ps |
| T1054 |
/workspace/coverage/default/9.flash_ctrl_mp_regions.2069920940 |
|
|
Dec 31 12:50:41 PM PST 23 |
Dec 31 12:52:43 PM PST 23 |
1239386500 ps |
| T292 |
/workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2405643968 |
|
|
Dec 31 12:50:47 PM PST 23 |
Dec 31 12:53:45 PM PST 23 |
10020005500 ps |
| T1055 |
/workspace/coverage/default/7.flash_ctrl_re_evict.4273147919 |
|
|
Dec 31 12:50:41 PM PST 23 |
Dec 31 12:51:24 PM PST 23 |
187428700 ps |
| T1056 |
/workspace/coverage/default/6.flash_ctrl_connect.3825639636 |
|
|
Dec 31 12:50:37 PM PST 23 |
Dec 31 12:51:02 PM PST 23 |
72658300 ps |
| T1057 |
/workspace/coverage/default/2.flash_ctrl_ro.4117581455 |
|
|
Dec 31 12:50:26 PM PST 23 |
Dec 31 12:52:15 PM PST 23 |
3972063800 ps |
| T1058 |
/workspace/coverage/default/6.flash_ctrl_intr_rd.3612417563 |
|
|
Dec 31 12:51:01 PM PST 23 |
Dec 31 12:54:00 PM PST 23 |
2248815300 ps |
| T1059 |
/workspace/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.4044456165 |
|
|
Dec 31 12:51:10 PM PST 23 |
Dec 31 12:52:08 PM PST 23 |
10045282000 ps |
| T1060 |
/workspace/coverage/default/16.flash_ctrl_alert_test.415217965 |
|
|
Dec 31 12:51:27 PM PST 23 |
Dec 31 12:51:48 PM PST 23 |
85117900 ps |
| T1061 |
/workspace/coverage/default/40.flash_ctrl_alert_test.3277805199 |
|
|
Dec 31 12:51:34 PM PST 23 |
Dec 31 12:51:56 PM PST 23 |
296763700 ps |
| T1062 |
/workspace/coverage/default/15.flash_ctrl_sec_info_access.4066602857 |
|
|
Dec 31 12:51:10 PM PST 23 |
Dec 31 12:52:30 PM PST 23 |
5637412200 ps |
| T1063 |
/workspace/coverage/default/15.flash_ctrl_rw_evict_all_en.2488048640 |
|
|
Dec 31 12:51:11 PM PST 23 |
Dec 31 12:51:52 PM PST 23 |
61046300 ps |
| T1064 |
/workspace/coverage/default/42.flash_ctrl_hw_sec_otp.222670080 |
|
|
Dec 31 12:51:45 PM PST 23 |
Dec 31 12:55:17 PM PST 23 |
2639198600 ps |
| T213 |
/workspace/coverage/default/3.flash_ctrl_phy_host_grant_err.1540928168 |
|
|
Dec 31 12:50:52 PM PST 23 |
Dec 31 12:51:07 PM PST 23 |
22559700 ps |
| T1065 |
/workspace/coverage/default/21.flash_ctrl_alert_test.636860809 |
|
|
Dec 31 12:51:15 PM PST 23 |
Dec 31 12:51:39 PM PST 23 |
164364700 ps |
| T1066 |
/workspace/coverage/default/1.flash_ctrl_rd_buff_evict.3339051483 |
|
|
Dec 31 12:50:09 PM PST 23 |
Dec 31 12:51:52 PM PST 23 |
988762700 ps |
| T1067 |
/workspace/coverage/default/28.flash_ctrl_connect.2415429702 |
|
|
Dec 31 12:51:19 PM PST 23 |
Dec 31 12:51:44 PM PST 23 |
16043900 ps |
| T1068 |
/workspace/coverage/default/18.flash_ctrl_rw_evict.1772318591 |
|
|
Dec 31 12:51:21 PM PST 23 |
Dec 31 12:52:03 PM PST 23 |
271150900 ps |
| T1069 |
/workspace/coverage/default/6.flash_ctrl_intr_wr.2825227518 |
|
|
Dec 31 12:50:50 PM PST 23 |
Dec 31 12:52:09 PM PST 23 |
3461415500 ps |
| T1070 |
/workspace/coverage/default/25.flash_ctrl_connect.1986465507 |
|
|
Dec 31 12:51:17 PM PST 23 |
Dec 31 12:51:44 PM PST 23 |
49209500 ps |
| T1071 |
/workspace/coverage/default/18.flash_ctrl_otp_reset.3978345244 |
|
|
Dec 31 12:51:10 PM PST 23 |
Dec 31 12:53:32 PM PST 23 |
128274000 ps |
| T1072 |
/workspace/coverage/default/17.flash_ctrl_wo.4174471333 |
|
|
Dec 31 12:51:22 PM PST 23 |
Dec 31 12:54:31 PM PST 23 |
3569235300 ps |
| T1073 |
/workspace/coverage/default/43.flash_ctrl_otp_reset.492412356 |
|
|
Dec 31 12:51:36 PM PST 23 |
Dec 31 12:53:58 PM PST 23 |
37590100 ps |
| T1074 |
/workspace/coverage/default/39.flash_ctrl_rw_evict.967851881 |
|
|
Dec 31 12:51:20 PM PST 23 |
Dec 31 12:51:59 PM PST 23 |
55204700 ps |
| T1075 |
/workspace/coverage/default/6.flash_ctrl_rw.3711275853 |
|
|
Dec 31 12:50:34 PM PST 23 |
Dec 31 12:59:32 PM PST 23 |
62152421600 ps |
| T1076 |
/workspace/coverage/default/50.flash_ctrl_connect.1636227899 |
|
|
Dec 31 12:51:45 PM PST 23 |
Dec 31 12:52:12 PM PST 23 |
46565600 ps |
| T1077 |
/workspace/coverage/default/23.flash_ctrl_otp_reset.176798100 |
|
|
Dec 31 12:51:15 PM PST 23 |
Dec 31 12:53:38 PM PST 23 |
124313600 ps |
| T208 |
/workspace/coverage/default/1.flash_ctrl_host_ctrl_arb.3447046898 |
|
|
Dec 31 12:50:14 PM PST 23 |
Dec 31 01:31:06 PM PST 23 |
251714992400 ps |
| T1078 |
/workspace/coverage/default/13.flash_ctrl_ro.1115749985 |
|
|
Dec 31 12:51:11 PM PST 23 |
Dec 31 12:52:56 PM PST 23 |
1673843000 ps |
| T1079 |
/workspace/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1415074860 |
|
|
Dec 31 12:51:31 PM PST 23 |
Dec 31 12:54:56 PM PST 23 |
8937882200 ps |
| T1080 |
/workspace/coverage/default/8.flash_ctrl_error_prog_win.2759932969 |
|
|
Dec 31 12:50:57 PM PST 23 |
Dec 31 01:03:42 PM PST 23 |
659036000 ps |
| T1081 |
/workspace/coverage/default/10.flash_ctrl_prog_reset.2444885053 |
|
|
Dec 31 12:51:05 PM PST 23 |
Dec 31 12:51:33 PM PST 23 |
18366800 ps |
| T1082 |
/workspace/coverage/default/42.flash_ctrl_disable.772879071 |
|
|
Dec 31 12:51:32 PM PST 23 |
Dec 31 12:52:01 PM PST 23 |
12209600 ps |
| T1083 |
/workspace/coverage/default/3.flash_ctrl_smoke.4084287072 |
|
|
Dec 31 12:50:26 PM PST 23 |
Dec 31 12:52:32 PM PST 23 |
222078400 ps |
| T1084 |
/workspace/coverage/default/0.flash_ctrl_rd_ooo.1172724445 |
|
|
Dec 31 12:50:18 PM PST 23 |
Dec 31 12:51:05 PM PST 23 |
114825100 ps |
| T1085 |
/workspace/coverage/default/46.flash_ctrl_otp_reset.3708355144 |
|
|
Dec 31 12:51:44 PM PST 23 |
Dec 31 12:54:09 PM PST 23 |
164562700 ps |
| T1086 |
/workspace/coverage/default/4.flash_ctrl_mp_regions.1665732808 |
|
|
Dec 31 12:50:30 PM PST 23 |
Dec 31 12:53:11 PM PST 23 |
3907563700 ps |
| T1087 |
/workspace/coverage/default/0.flash_ctrl_rw_serr.3973154647 |
|
|
Dec 31 12:49:57 PM PST 23 |
Dec 31 12:57:55 PM PST 23 |
12281763800 ps |
| T1088 |
/workspace/coverage/default/1.flash_ctrl_rw_serr.2731698668 |
|
|
Dec 31 12:50:27 PM PST 23 |
Dec 31 12:59:31 PM PST 23 |
13837310200 ps |
| T1089 |
/workspace/coverage/default/26.flash_ctrl_connect.2525792744 |
|
|
Dec 31 12:51:38 PM PST 23 |
Dec 31 12:52:07 PM PST 23 |
54524300 ps |
| T1090 |
/workspace/coverage/default/38.flash_ctrl_alert_test.480376907 |
|
|
Dec 31 12:51:32 PM PST 23 |
Dec 31 12:52:01 PM PST 23 |
74170300 ps |
| T1091 |
/workspace/coverage/default/3.flash_ctrl_intr_rd.351887393 |
|
|
Dec 31 12:50:26 PM PST 23 |
Dec 31 12:53:02 PM PST 23 |
7775151100 ps |
| T1092 |
/workspace/coverage/default/4.flash_ctrl_full_mem_access.3800933785 |
|
|
Dec 31 12:50:26 PM PST 23 |
Dec 31 01:33:11 PM PST 23 |
81110925400 ps |
| T1093 |
/workspace/coverage/default/3.flash_ctrl_stress_all.4205139447 |
|
|
Dec 31 12:50:52 PM PST 23 |
Dec 31 12:54:30 PM PST 23 |
464834700 ps |
| T1094 |
/workspace/coverage/default/71.flash_ctrl_otp_reset.2372332150 |
|
|
Dec 31 12:51:43 PM PST 23 |
Dec 31 12:53:45 PM PST 23 |
36227100 ps |
| T1095 |
/workspace/coverage/default/9.flash_ctrl_rw_evict.245350948 |
|
|
Dec 31 12:51:09 PM PST 23 |
Dec 31 12:51:51 PM PST 23 |
77215800 ps |
| T1096 |
/workspace/coverage/default/25.flash_ctrl_rw_evict_all_en.3394436189 |
|
|
Dec 31 12:51:19 PM PST 23 |
Dec 31 12:51:59 PM PST 23 |
29216900 ps |
| T1097 |
/workspace/coverage/default/56.flash_ctrl_otp_reset.1929847517 |
|
|
Dec 31 12:51:35 PM PST 23 |
Dec 31 12:53:38 PM PST 23 |
157258600 ps |
| T1098 |
/workspace/coverage/default/4.flash_ctrl_sw_op.3255247118 |
|
|
Dec 31 12:50:19 PM PST 23 |
Dec 31 12:50:52 PM PST 23 |
84338400 ps |
| T1099 |
/workspace/coverage/default/1.flash_ctrl_smoke_hw.171460296 |
|
|
Dec 31 12:50:01 PM PST 23 |
Dec 31 12:50:36 PM PST 23 |
38351700 ps |
| T1100 |
/workspace/coverage/default/2.flash_ctrl_rw_serr.2738172696 |
|
|
Dec 31 12:50:14 PM PST 23 |
Dec 31 12:59:36 PM PST 23 |
4692545400 ps |
| T1101 |
/workspace/coverage/default/37.flash_ctrl_disable.3643252230 |
|
|
Dec 31 12:51:44 PM PST 23 |
Dec 31 12:52:19 PM PST 23 |
25622400 ps |
| T1102 |
/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.1051431658 |
|
|
Dec 31 12:51:23 PM PST 23 |
Dec 31 01:05:16 PM PST 23 |
80151825400 ps |
| T1103 |
/workspace/coverage/default/46.flash_ctrl_sec_info_access.3129989911 |
|
|
Dec 31 12:51:51 PM PST 23 |
Dec 31 12:53:08 PM PST 23 |
2288208800 ps |
| T1104 |
/workspace/coverage/default/17.flash_ctrl_rand_ops.2744054814 |
|
|
Dec 31 12:51:06 PM PST 23 |
Dec 31 12:57:59 PM PST 23 |
944693700 ps |
| T1105 |
/workspace/coverage/default/47.flash_ctrl_alert_test.2609215015 |
|
|
Dec 31 12:51:18 PM PST 23 |
Dec 31 12:51:41 PM PST 23 |
45802600 ps |
| T1106 |
/workspace/coverage/default/47.flash_ctrl_disable.3284819496 |
|
|
Dec 31 12:51:33 PM PST 23 |
Dec 31 12:52:04 PM PST 23 |
18275300 ps |
| T1107 |
/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3131601150 |
|
|
Dec 31 12:50:44 PM PST 23 |
Dec 31 12:54:40 PM PST 23 |
9330356100 ps |
| T1108 |
/workspace/coverage/default/14.flash_ctrl_connect.3100853083 |
|
|
Dec 31 12:51:35 PM PST 23 |
Dec 31 12:52:01 PM PST 23 |
25569900 ps |
| T1109 |
/workspace/coverage/default/2.flash_ctrl_intr_wr.3721769505 |
|
|
Dec 31 12:50:12 PM PST 23 |
Dec 31 12:52:11 PM PST 23 |
9484390500 ps |
| T1110 |
/workspace/coverage/default/6.flash_ctrl_rw_evict_all_en.417362057 |
|
|
Dec 31 12:50:36 PM PST 23 |
Dec 31 12:51:18 PM PST 23 |
96854200 ps |
| T1111 |
/workspace/coverage/default/14.flash_ctrl_intr_rd_slow_flash.546169249 |
|
|
Dec 31 12:51:24 PM PST 23 |
Dec 31 12:55:04 PM PST 23 |
18595991200 ps |
| T1112 |
/workspace/coverage/default/19.flash_ctrl_hw_read_seed_err.1127355499 |
|
|
Dec 31 12:51:24 PM PST 23 |
Dec 31 12:51:46 PM PST 23 |
24917500 ps |
| T1113 |
/workspace/coverage/default/36.flash_ctrl_smoke.1418278331 |
|
|
Dec 31 12:51:38 PM PST 23 |
Dec 31 12:52:41 PM PST 23 |
35179900 ps |
| T1114 |
/workspace/coverage/default/4.flash_ctrl_rw_serr.3739571801 |
|
|
Dec 31 12:51:05 PM PST 23 |
Dec 31 01:01:17 PM PST 23 |
3774466200 ps |
| T375 |
/workspace/coverage/default/39.flash_ctrl_sec_info_access.3673176389 |
|
|
Dec 31 12:51:37 PM PST 23 |
Dec 31 12:52:54 PM PST 23 |
2571705200 ps |
| T1115 |
/workspace/coverage/default/10.flash_ctrl_lcmgr_intg.2294143647 |
|
|
Dec 31 12:50:27 PM PST 23 |
Dec 31 12:50:43 PM PST 23 |
82741800 ps |
| T1116 |
/workspace/coverage/default/5.flash_ctrl_rw_derr.2357119120 |
|
|
Dec 31 12:50:56 PM PST 23 |
Dec 31 01:00:25 PM PST 23 |
5047520400 ps |
| T1117 |
/workspace/coverage/default/23.flash_ctrl_sec_info_access.2471256637 |
|
|
Dec 31 12:51:45 PM PST 23 |
Dec 31 12:53:12 PM PST 23 |
4103451000 ps |
| T1118 |
/workspace/coverage/default/38.flash_ctrl_otp_reset.1024789467 |
|
|
Dec 31 12:51:35 PM PST 23 |
Dec 31 12:53:59 PM PST 23 |
37214200 ps |
| T1119 |
/workspace/coverage/default/32.flash_ctrl_rw_evict_all_en.1113747770 |
|
|
Dec 31 12:51:16 PM PST 23 |
Dec 31 12:51:56 PM PST 23 |
132842600 ps |
| T1120 |
/workspace/coverage/default/3.flash_ctrl_full_mem_access.147171555 |
|
|
Dec 31 12:50:27 PM PST 23 |
Dec 31 01:29:42 PM PST 23 |
93154272500 ps |
| T1121 |
/workspace/coverage/default/4.flash_ctrl_rw_evict.3761898482 |
|
|
Dec 31 12:50:41 PM PST 23 |
Dec 31 12:51:19 PM PST 23 |
36479500 ps |
| T1122 |
/workspace/coverage/default/12.flash_ctrl_rw_evict_all_en.711250763 |
|
|
Dec 31 12:51:09 PM PST 23 |
Dec 31 12:51:48 PM PST 23 |
55326000 ps |
| T1123 |
/workspace/coverage/default/18.flash_ctrl_ro.1548916759 |
|
|
Dec 31 12:51:20 PM PST 23 |
Dec 31 12:53:11 PM PST 23 |
911582900 ps |
| T1124 |
/workspace/coverage/default/39.flash_ctrl_rw_evict_all_en.931742776 |
|
|
Dec 31 12:51:34 PM PST 23 |
Dec 31 12:52:13 PM PST 23 |
37558300 ps |
| T1125 |
/workspace/coverage/default/7.flash_ctrl_fetch_code.2462132515 |
|
|
Dec 31 12:50:37 PM PST 23 |
Dec 31 12:51:06 PM PST 23 |
1338562400 ps |
| T1126 |
/workspace/coverage/default/2.flash_ctrl_invalid_op.1260978992 |
|
|
Dec 31 12:50:37 PM PST 23 |
Dec 31 12:52:13 PM PST 23 |
1949228400 ps |
| T33 |
/workspace/coverage/default/2.flash_ctrl_access_after_disable.267172813 |
|
|
Dec 31 12:50:24 PM PST 23 |
Dec 31 12:50:39 PM PST 23 |
20577500 ps |
| T230 |
/workspace/coverage/default/4.flash_ctrl_phy_ack_consistency.2817655078 |
|
|
Dec 31 12:50:58 PM PST 23 |
Dec 31 12:51:24 PM PST 23 |
25125200 ps |
| T114 |
/workspace/coverage/default/3.flash_ctrl_sec_cm.2283850353 |
|
|
Dec 31 12:50:24 PM PST 23 |
Dec 31 02:08:46 PM PST 23 |
1911123400 ps |
| T1127 |
/workspace/coverage/default/4.flash_ctrl_ro_serr.167156520 |
|
|
Dec 31 12:50:35 PM PST 23 |
Dec 31 12:52:37 PM PST 23 |
481347200 ps |
| T1128 |
/workspace/coverage/default/2.flash_ctrl_prog_reset.3998556923 |
|
|
Dec 31 12:50:26 PM PST 23 |
Dec 31 12:50:43 PM PST 23 |
78784100 ps |
| T1129 |
/workspace/coverage/default/57.flash_ctrl_connect.641975545 |
|
|
Dec 31 12:51:36 PM PST 23 |
Dec 31 12:52:05 PM PST 23 |
43712900 ps |
| T1130 |
/workspace/coverage/default/28.flash_ctrl_prog_reset.3950890859 |
|
|
Dec 31 12:51:24 PM PST 23 |
Dec 31 12:51:47 PM PST 23 |
42441200 ps |
| T1131 |
/workspace/coverage/default/8.flash_ctrl_ro.2563463590 |
|
|
Dec 31 12:50:53 PM PST 23 |
Dec 31 12:52:21 PM PST 23 |
2647301100 ps |
| T1132 |
/workspace/coverage/default/4.flash_ctrl_error_prog_type.1978559718 |
|
|
Dec 31 12:50:20 PM PST 23 |
Dec 31 01:37:01 PM PST 23 |
4463777900 ps |
| T1133 |
/workspace/coverage/default/16.flash_ctrl_rw.3912910502 |
|
|
Dec 31 12:51:07 PM PST 23 |
Dec 31 01:00:09 PM PST 23 |
16839934400 ps |
| T1134 |
/workspace/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3601809528 |
|
|
Dec 31 12:51:36 PM PST 23 |
Dec 31 12:54:48 PM PST 23 |
8287966800 ps |
| T1135 |
/workspace/coverage/default/38.flash_ctrl_connect.1720355908 |
|
|
Dec 31 12:51:37 PM PST 23 |
Dec 31 12:52:05 PM PST 23 |
14345400 ps |
| T1136 |
/workspace/coverage/default/5.flash_ctrl_hw_sec_otp.517722573 |
|
|
Dec 31 12:50:44 PM PST 23 |
Dec 31 12:52:05 PM PST 23 |
3984358400 ps |
| T1137 |
/workspace/coverage/default/49.flash_ctrl_hw_sec_otp.180618067 |
|
|
Dec 31 12:51:35 PM PST 23 |
Dec 31 12:53:16 PM PST 23 |
8857542900 ps |
| T383 |
/workspace/coverage/default/0.flash_ctrl_invalid_op.58927425 |
|
|
Dec 31 12:50:00 PM PST 23 |
Dec 31 12:51:07 PM PST 23 |
3331401000 ps |
| T1138 |
/workspace/coverage/default/19.flash_ctrl_invalid_op.658212001 |
|
|
Dec 31 12:51:19 PM PST 23 |
Dec 31 12:52:41 PM PST 23 |
13589939500 ps |
| T1139 |
/workspace/coverage/default/6.flash_ctrl_ro_serr.3599729994 |
|
|
Dec 31 12:50:50 PM PST 23 |
Dec 31 12:52:40 PM PST 23 |
1059997000 ps |
| T1140 |
/workspace/coverage/default/14.flash_ctrl_sec_info_access.3359831925 |
|
|
Dec 31 12:51:37 PM PST 23 |
Dec 31 12:52:50 PM PST 23 |
4641446900 ps |
| T1141 |
/workspace/coverage/default/9.flash_ctrl_rw.3377707101 |
|
|
Dec 31 12:50:37 PM PST 23 |
Dec 31 12:59:45 PM PST 23 |
25744283100 ps |
| T1142 |
/workspace/coverage/default/10.flash_ctrl_wo.2240973750 |
|
|
Dec 31 12:50:40 PM PST 23 |
Dec 31 12:53:22 PM PST 23 |
1812026500 ps |
| T1143 |
/workspace/coverage/default/26.flash_ctrl_alert_test.1020241693 |
|
|
Dec 31 12:51:48 PM PST 23 |
Dec 31 12:52:12 PM PST 23 |
41823800 ps |
| T1144 |
/workspace/coverage/default/0.flash_ctrl_lcmgr_intg.2505984870 |
|
|
Dec 31 12:50:34 PM PST 23 |
Dec 31 12:51:00 PM PST 23 |
48343300 ps |
| T182 |
/workspace/coverage/default/1.flash_ctrl_wr_intg.3673683734 |
|
|
Dec 31 12:50:39 PM PST 23 |
Dec 31 12:51:02 PM PST 23 |
51762200 ps |
| T1145 |
/workspace/coverage/default/60.flash_ctrl_connect.1100711370 |
|
|
Dec 31 12:51:54 PM PST 23 |
Dec 31 12:52:18 PM PST 23 |
14272300 ps |
| T1146 |
/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.2983996787 |
|
|
Dec 31 12:51:27 PM PST 23 |
Dec 31 12:53:35 PM PST 23 |
2787325600 ps |
| T1147 |
/workspace/coverage/default/10.flash_ctrl_hw_read_seed_err.511409637 |
|
|
Dec 31 12:50:56 PM PST 23 |
Dec 31 12:51:12 PM PST 23 |
60027500 ps |
| T1148 |
/workspace/coverage/default/0.flash_ctrl_error_mp.606477977 |
|
|
Dec 31 12:50:01 PM PST 23 |
Dec 31 01:31:32 PM PST 23 |
38447620800 ps |
| T1149 |
/workspace/coverage/default/1.flash_ctrl_erase_suspend.2871654321 |
|
|
Dec 31 12:50:14 PM PST 23 |
Dec 31 12:57:08 PM PST 23 |
4463182700 ps |
| T1150 |
/workspace/coverage/default/17.flash_ctrl_hw_rma_reset.2388597569 |
|
|
Dec 31 12:51:25 PM PST 23 |
Dec 31 01:03:46 PM PST 23 |
160174575500 ps |
| T1151 |
/workspace/coverage/default/22.flash_ctrl_disable.4025361671 |
|
|
Dec 31 12:51:10 PM PST 23 |
Dec 31 12:51:42 PM PST 23 |
10882200 ps |
| T1152 |
/workspace/coverage/default/2.flash_ctrl_rw_evict.2370813366 |
|
|
Dec 31 12:50:33 PM PST 23 |
Dec 31 12:51:17 PM PST 23 |
30771200 ps |
| T1153 |
/workspace/coverage/default/39.flash_ctrl_disable.1636337329 |
|
|
Dec 31 12:51:28 PM PST 23 |
Dec 31 12:51:57 PM PST 23 |
14828000 ps |
| T1154 |
/workspace/coverage/default/19.flash_ctrl_rand_ops.3746323332 |
|
|
Dec 31 12:51:18 PM PST 23 |
Dec 31 01:02:51 PM PST 23 |
802306500 ps |
| T149 |
/workspace/coverage/default/18.flash_ctrl_hw_rma_reset.1685115003 |
|
|
Dec 31 12:51:18 PM PST 23 |
Dec 31 01:04:11 PM PST 23 |
120150067900 ps |
| T1155 |
/workspace/coverage/default/16.flash_ctrl_prog_reset.1936263824 |
|
|
Dec 31 12:51:06 PM PST 23 |
Dec 31 12:51:34 PM PST 23 |
72800900 ps |
| T1156 |
/workspace/coverage/default/16.flash_ctrl_disable.3133263929 |
|
|
Dec 31 12:51:05 PM PST 23 |
Dec 31 12:51:41 PM PST 23 |
27705800 ps |
| T1157 |
/workspace/coverage/default/5.flash_ctrl_ro_serr.595736809 |
|
|
Dec 31 12:50:59 PM PST 23 |
Dec 31 12:53:16 PM PST 23 |
822009000 ps |
| T1158 |
/workspace/coverage/default/8.flash_ctrl_lcmgr_intg.1802424915 |
|
|
Dec 31 12:51:13 PM PST 23 |
Dec 31 12:51:36 PM PST 23 |
211620000 ps |
| T1159 |
/workspace/coverage/default/20.flash_ctrl_smoke.1595469012 |
|
|
Dec 31 12:51:19 PM PST 23 |
Dec 31 12:53:29 PM PST 23 |
84074000 ps |
| T1160 |
/workspace/coverage/default/48.flash_ctrl_smoke.3470025755 |
|
|
Dec 31 12:51:32 PM PST 23 |
Dec 31 12:52:31 PM PST 23 |
26698500 ps |
| T1161 |
/workspace/coverage/default/3.flash_ctrl_wo.2672307852 |
|
|
Dec 31 12:50:22 PM PST 23 |
Dec 31 12:53:19 PM PST 23 |
9095362600 ps |
| T1162 |
/workspace/coverage/default/35.flash_ctrl_disable.1577365731 |
|
|
Dec 31 12:51:51 PM PST 23 |
Dec 31 12:52:21 PM PST 23 |
13799600 ps |
| T296 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.46858147 |
|
|
Dec 31 12:41:10 PM PST 23 |
Dec 31 12:41:29 PM PST 23 |
578158900 ps |
| T239 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.3581002984 |
|
|
Dec 31 12:41:29 PM PST 23 |
Dec 31 12:41:47 PM PST 23 |
74648600 ps |
| T1163 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.939419241 |
|
|
Dec 31 12:41:32 PM PST 23 |
Dec 31 12:41:46 PM PST 23 |
101265600 ps |
| T1164 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2429066864 |
|
|
Dec 31 12:41:40 PM PST 23 |
Dec 31 12:42:00 PM PST 23 |
91130900 ps |
| T1165 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2595950342 |
|
|
Dec 31 12:41:27 PM PST 23 |
Dec 31 12:41:45 PM PST 23 |
71838000 ps |
| T1166 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.134391956 |
|
|
Dec 31 12:41:39 PM PST 23 |
Dec 31 12:41:58 PM PST 23 |
53505500 ps |
| T297 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2706957056 |
|
|
Dec 31 12:41:42 PM PST 23 |
Dec 31 12:42:20 PM PST 23 |
325007800 ps |
| T1167 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2382696141 |
|
|
Dec 31 12:41:16 PM PST 23 |
Dec 31 12:41:33 PM PST 23 |
45089300 ps |
| T1168 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.137280634 |
|
|
Dec 31 12:41:08 PM PST 23 |
Dec 31 12:41:24 PM PST 23 |
20152700 ps |
| T1169 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.2781024811 |
|
|
Dec 31 12:41:07 PM PST 23 |
Dec 31 12:41:22 PM PST 23 |
29035300 ps |
| T1170 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.1625850175 |
|
|
Dec 31 12:41:39 PM PST 23 |
Dec 31 12:41:58 PM PST 23 |
15273800 ps |
| T1171 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1352817303 |
|
|
Dec 31 12:41:41 PM PST 23 |
Dec 31 12:42:01 PM PST 23 |
66602200 ps |
| T1172 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2803518669 |
|
|
Dec 31 12:41:14 PM PST 23 |
Dec 31 12:41:28 PM PST 23 |
26197300 ps |
| T258 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3502478734 |
|
|
Dec 31 12:41:38 PM PST 23 |
Dec 31 12:49:27 PM PST 23 |
1559070900 ps |
| T1173 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.1308215013 |
|
|
Dec 31 12:41:20 PM PST 23 |
Dec 31 12:41:37 PM PST 23 |
13394500 ps |
| T1174 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.1085769260 |
|
|
Dec 31 12:41:38 PM PST 23 |
Dec 31 12:41:58 PM PST 23 |
41611700 ps |
| T1175 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.1643878006 |
|
|
Dec 31 12:41:40 PM PST 23 |
Dec 31 12:41:58 PM PST 23 |
17449200 ps |
| T1176 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.3599706263 |
|
|
Dec 31 12:41:22 PM PST 23 |
Dec 31 12:41:36 PM PST 23 |
98285100 ps |
| T322 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.4226255868 |
|
|
Dec 31 12:41:15 PM PST 23 |
Dec 31 12:48:53 PM PST 23 |
654034700 ps |
| T1177 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1814388315 |
|
|
Dec 31 12:41:09 PM PST 23 |
Dec 31 12:41:25 PM PST 23 |
21456700 ps |
| T301 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.808418901 |
|
|
Dec 31 12:41:36 PM PST 23 |
Dec 31 12:42:37 PM PST 23 |
6457324300 ps |
| T1178 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.3119688365 |
|
|
Dec 31 12:41:49 PM PST 23 |
Dec 31 12:42:04 PM PST 23 |
14856000 ps |
| T1179 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2508902763 |
|
|
Dec 31 12:41:13 PM PST 23 |
Dec 31 12:41:27 PM PST 23 |
49026100 ps |
| T1180 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.650177460 |
|
|
Dec 31 12:41:49 PM PST 23 |
Dec 31 12:42:08 PM PST 23 |
24750900 ps |
| T1181 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2383014672 |
|
|
Dec 31 12:41:06 PM PST 23 |
Dec 31 12:41:23 PM PST 23 |
14719800 ps |
| T1182 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2497882333 |
|
|
Dec 31 12:41:17 PM PST 23 |
Dec 31 12:41:34 PM PST 23 |
215004100 ps |
| T249 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3270476361 |
|
|
Dec 31 12:40:56 PM PST 23 |
Dec 31 12:41:14 PM PST 23 |
17346200 ps |
| T317 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.4146321953 |
|
|
Dec 31 12:41:21 PM PST 23 |
Dec 31 12:48:54 PM PST 23 |
494678400 ps |
| T1183 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3137012532 |
|
|
Dec 31 12:41:43 PM PST 23 |
Dec 31 12:42:01 PM PST 23 |
84946300 ps |
| T1184 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.721111158 |
|
|
Dec 31 12:41:23 PM PST 23 |
Dec 31 12:41:39 PM PST 23 |
44497600 ps |
| T261 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3911190279 |
|
|
Dec 31 12:41:19 PM PST 23 |
Dec 31 12:41:39 PM PST 23 |
77009900 ps |
| T1185 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1400584751 |
|
|
Dec 31 12:41:32 PM PST 23 |
Dec 31 12:41:54 PM PST 23 |
336247000 ps |
| T1186 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3577884215 |
|
|
Dec 31 12:41:10 PM PST 23 |
Dec 31 12:41:26 PM PST 23 |
16457200 ps |
| T1187 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1960609717 |
|
|
Dec 31 12:41:07 PM PST 23 |
Dec 31 12:41:26 PM PST 23 |
53636400 ps |
| T1188 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.301004691 |
|
|
Dec 31 12:41:38 PM PST 23 |
Dec 31 12:42:02 PM PST 23 |
36885200 ps |
| T260 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.503321567 |
|
|
Dec 31 12:41:37 PM PST 23 |
Dec 31 12:42:05 PM PST 23 |
206301000 ps |
| T1189 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.195458924 |
|
|
Dec 31 12:41:02 PM PST 23 |
Dec 31 12:41:22 PM PST 23 |
180542800 ps |
| T1190 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3062071535 |
|
|
Dec 31 12:41:50 PM PST 23 |
Dec 31 12:42:04 PM PST 23 |
44035200 ps |
| T1191 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1556507743 |
|
|
Dec 31 12:41:22 PM PST 23 |
Dec 31 12:41:38 PM PST 23 |
96532200 ps |
| T264 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1497809882 |
|
|
Dec 31 12:41:14 PM PST 23 |
Dec 31 12:41:35 PM PST 23 |
199307000 ps |
| T315 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3386993683 |
|
|
Dec 31 12:41:23 PM PST 23 |
Dec 31 12:53:58 PM PST 23 |
354302600 ps |
| T1192 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.830068878 |
|
|
Dec 31 12:41:08 PM PST 23 |
Dec 31 12:41:27 PM PST 23 |
55783400 ps |
| T1193 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3173989339 |
|
|
Dec 31 12:41:29 PM PST 23 |
Dec 31 12:42:02 PM PST 23 |
45055300 ps |
| T1194 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2710239816 |
|
|
Dec 31 12:41:29 PM PST 23 |
Dec 31 12:42:05 PM PST 23 |
1069427300 ps |
| T1195 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.249252221 |
|
|
Dec 31 12:42:02 PM PST 23 |
Dec 31 12:42:17 PM PST 23 |
28120900 ps |
| T1196 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.269141033 |
|
|
Dec 31 12:41:29 PM PST 23 |
Dec 31 12:41:43 PM PST 23 |
78440300 ps |
| T1197 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.868558224 |
|
|
Dec 31 12:41:46 PM PST 23 |
Dec 31 12:42:02 PM PST 23 |
42698600 ps |
| T1198 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.624556269 |
|
|
Dec 31 12:41:18 PM PST 23 |
Dec 31 12:41:34 PM PST 23 |
190082800 ps |
| T1199 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1839969508 |
|
|
Dec 31 12:41:05 PM PST 23 |
Dec 31 12:41:20 PM PST 23 |
39526000 ps |
| T302 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1295775270 |
|
|
Dec 31 12:41:13 PM PST 23 |
Dec 31 12:41:30 PM PST 23 |
411706900 ps |
| T1200 |
/workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1069010010 |
|
|
Dec 31 12:41:55 PM PST 23 |
Dec 31 12:42:10 PM PST 23 |
107181400 ps |
| T1201 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.2840598105 |
|
|
Dec 31 12:41:51 PM PST 23 |
Dec 31 12:42:06 PM PST 23 |
25814000 ps |
| T1202 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2022288264 |
|
|
Dec 31 12:41:51 PM PST 23 |
Dec 31 12:42:06 PM PST 23 |
49125700 ps |
| T1203 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2212178568 |
|
|
Dec 31 12:41:29 PM PST 23 |
Dec 31 12:42:04 PM PST 23 |
131954300 ps |
| T1204 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_rw.3519685930 |
|
|
Dec 31 12:41:34 PM PST 23 |
Dec 31 12:41:58 PM PST 23 |
27504900 ps |
| T1205 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2981557775 |
|
|
Dec 31 12:42:01 PM PST 23 |
Dec 31 12:42:16 PM PST 23 |
25656500 ps |
| T262 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.4043403956 |
|
|
Dec 31 12:41:43 PM PST 23 |
Dec 31 12:42:06 PM PST 23 |
400888200 ps |
| T1206 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2300801923 |
|
|
Dec 31 12:41:44 PM PST 23 |
Dec 31 12:42:02 PM PST 23 |
28607600 ps |
| T1207 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3896835477 |
|
|
Dec 31 12:41:38 PM PST 23 |
Dec 31 12:41:58 PM PST 23 |
34209700 ps |
| T1208 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.461324066 |
|
|
Dec 31 12:41:32 PM PST 23 |
Dec 31 12:41:50 PM PST 23 |
22533500 ps |
| T1209 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.3507446682 |
|
|
Dec 31 12:41:36 PM PST 23 |
Dec 31 12:41:58 PM PST 23 |
32394000 ps |
| T318 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4099705028 |
|
|
Dec 31 12:41:57 PM PST 23 |
Dec 31 12:56:57 PM PST 23 |
347418800 ps |
| T1210 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1627366165 |
|
|
Dec 31 12:41:32 PM PST 23 |
Dec 31 12:41:50 PM PST 23 |
184499200 ps |
| T1211 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.2165574437 |
|
|
Dec 31 12:40:59 PM PST 23 |
Dec 31 12:41:31 PM PST 23 |
76286600 ps |
| T1212 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3399338266 |
|
|
Dec 31 12:41:55 PM PST 23 |
Dec 31 12:42:14 PM PST 23 |
34051300 ps |
| T1213 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.176718928 |
|
|
Dec 31 12:41:30 PM PST 23 |
Dec 31 12:41:46 PM PST 23 |
12765900 ps |
| T1214 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2744825218 |
|
|
Dec 31 12:41:57 PM PST 23 |
Dec 31 12:42:19 PM PST 23 |
34571900 ps |
| T1215 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.4113282390 |
|
|
Dec 31 12:41:56 PM PST 23 |
Dec 31 12:42:11 PM PST 23 |
15495100 ps |
| T1216 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.893531562 |
|
|
Dec 31 12:41:33 PM PST 23 |
Dec 31 12:42:10 PM PST 23 |
60003400 ps |
| T1217 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2587678889 |
|
|
Dec 31 12:41:21 PM PST 23 |
Dec 31 12:41:35 PM PST 23 |
43458200 ps |
| T263 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1013258832 |
|
|
Dec 31 12:41:48 PM PST 23 |
Dec 31 12:42:07 PM PST 23 |
47287800 ps |
| T1218 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3907218802 |
|
|
Dec 31 12:41:49 PM PST 23 |
Dec 31 12:42:04 PM PST 23 |
54207400 ps |
| T1219 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1378876354 |
|
|
Dec 31 12:41:52 PM PST 23 |
Dec 31 12:42:14 PM PST 23 |
36935900 ps |
| T1220 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3408331366 |
|
|
Dec 31 12:40:54 PM PST 23 |
Dec 31 12:41:11 PM PST 23 |
28570500 ps |
| T265 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.2532038785 |
|
|
Dec 31 12:41:46 PM PST 23 |
Dec 31 12:56:55 PM PST 23 |
10878497700 ps |
| T1221 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.612625114 |
|
|
Dec 31 12:41:18 PM PST 23 |
Dec 31 12:41:36 PM PST 23 |
160551700 ps |
| T303 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1761153165 |
|
|
Dec 31 12:41:36 PM PST 23 |
Dec 31 12:42:00 PM PST 23 |
50911700 ps |
| T1222 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.4246125491 |
|
|
Dec 31 12:41:51 PM PST 23 |
Dec 31 12:42:06 PM PST 23 |
42272900 ps |
| T321 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.145280030 |
|
|
Dec 31 12:40:59 PM PST 23 |
Dec 31 12:48:35 PM PST 23 |
638850300 ps |
| T1223 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.775507407 |
|
|
Dec 31 12:40:59 PM PST 23 |
Dec 31 12:41:19 PM PST 23 |
125210700 ps |
| T324 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1194076054 |
|
|
Dec 31 12:41:13 PM PST 23 |
Dec 31 12:48:48 PM PST 23 |
912328000 ps |
| T1224 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3188717017 |
|
|
Dec 31 12:41:36 PM PST 23 |
Dec 31 12:42:00 PM PST 23 |
71476500 ps |
| T1225 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.3762749706 |
|
|
Dec 31 12:41:27 PM PST 23 |
Dec 31 12:41:41 PM PST 23 |
30464300 ps |
| T1226 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.762080750 |
|
|
Dec 31 12:40:59 PM PST 23 |
Dec 31 12:41:40 PM PST 23 |
48221800 ps |
| T1227 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1033414751 |
|
|
Dec 31 12:41:18 PM PST 23 |
Dec 31 12:41:34 PM PST 23 |
14721800 ps |
| T304 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3430030301 |
|
|
Dec 31 12:41:55 PM PST 23 |
Dec 31 12:42:26 PM PST 23 |
203632900 ps |
| T1228 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.3540007233 |
|
|
Dec 31 12:41:14 PM PST 23 |
Dec 31 12:41:31 PM PST 23 |
35535000 ps |
| T250 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.201574490 |
|
|
Dec 31 12:41:20 PM PST 23 |
Dec 31 12:41:35 PM PST 23 |
59582200 ps |
| T1229 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3040195947 |
|
|
Dec 31 12:41:27 PM PST 23 |
Dec 31 12:41:45 PM PST 23 |
97708100 ps |
| T1230 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3978118847 |
|
|
Dec 31 12:41:10 PM PST 23 |
Dec 31 12:41:27 PM PST 23 |
18368800 ps |
| T1231 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3052423093 |
|
|
Dec 31 12:41:00 PM PST 23 |
Dec 31 12:41:18 PM PST 23 |
11554400 ps |
| T1232 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2486452186 |
|
|
Dec 31 12:41:49 PM PST 23 |
Dec 31 12:49:23 PM PST 23 |
984045100 ps |
| T1233 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.586553851 |
|
|
Dec 31 12:41:14 PM PST 23 |
Dec 31 12:41:44 PM PST 23 |
128808100 ps |
| T1234 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2425237876 |
|
|
Dec 31 12:41:41 PM PST 23 |
Dec 31 12:41:58 PM PST 23 |
92658300 ps |
| T1235 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1245523348 |
|
|
Dec 31 12:42:04 PM PST 23 |
Dec 31 12:42:18 PM PST 23 |
24429000 ps |
| T1236 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1607243716 |
|
|
Dec 31 12:40:59 PM PST 23 |
Dec 31 12:41:35 PM PST 23 |
112002100 ps |
| T305 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.12686461 |
|
|
Dec 31 12:41:11 PM PST 23 |
Dec 31 12:41:30 PM PST 23 |
99480900 ps |
| T1237 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.1527287566 |
|
|
Dec 31 12:41:30 PM PST 23 |
Dec 31 12:41:48 PM PST 23 |
70680700 ps |
| T1238 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.3473078501 |
|
|
Dec 31 12:41:42 PM PST 23 |
Dec 31 12:42:00 PM PST 23 |
47937600 ps |
| T1239 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_intr_test.3524167765 |
|
|
Dec 31 12:41:46 PM PST 23 |
Dec 31 12:42:02 PM PST 23 |
124675100 ps |
| T1240 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.498159805 |
|
|
Dec 31 12:42:17 PM PST 23 |
Dec 31 12:42:31 PM PST 23 |
15653100 ps |
| T1241 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.2579623497 |
|
|
Dec 31 12:41:52 PM PST 23 |
Dec 31 12:42:07 PM PST 23 |
55257000 ps |
| T1242 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.3977885244 |
|
|
Dec 31 12:41:42 PM PST 23 |
Dec 31 12:42:04 PM PST 23 |
212284200 ps |
| T1243 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3266473703 |
|
|
Dec 31 12:41:16 PM PST 23 |
Dec 31 12:41:35 PM PST 23 |
27401700 ps |
| T1244 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1362681244 |
|
|
Dec 31 12:41:33 PM PST 23 |
Dec 31 12:41:50 PM PST 23 |
155497000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1834276251 |
|
|
Dec 31 12:41:51 PM PST 23 |
Dec 31 12:42:09 PM PST 23 |
401553500 ps |
| T1246 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.4040147076 |
|
|
Dec 31 12:41:35 PM PST 23 |
Dec 31 12:41:58 PM PST 23 |
1396332900 ps |
| T319 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2209748745 |
|
|
Dec 31 12:41:26 PM PST 23 |
Dec 31 12:49:03 PM PST 23 |
1519113500 ps |
| T1247 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.3955778805 |
|
|
Dec 31 12:41:41 PM PST 23 |
Dec 31 12:41:59 PM PST 23 |
122793400 ps |
| T1248 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3558167612 |
|
|
Dec 31 12:41:08 PM PST 23 |
Dec 31 12:41:28 PM PST 23 |
62364900 ps |
| T316 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.353381452 |
|
|
Dec 31 12:41:17 PM PST 23 |
Dec 31 12:56:25 PM PST 23 |
1311176000 ps |
| T1249 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.3213858308 |
|
|
Dec 31 12:41:21 PM PST 23 |
Dec 31 12:41:38 PM PST 23 |
26288300 ps |
| T1250 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3589192039 |
|
|
Dec 31 12:41:51 PM PST 23 |
Dec 31 12:42:11 PM PST 23 |
131971200 ps |
| T1251 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2860260386 |
|
|
Dec 31 12:40:52 PM PST 23 |
Dec 31 12:42:12 PM PST 23 |
4849099000 ps |
| T1252 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3139194551 |
|
|
Dec 31 12:41:46 PM PST 23 |
Dec 31 12:42:08 PM PST 23 |
24369600 ps |