Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	330511	1		T53	1		T54	1		T138	1
all_values[1]	330511	1		T53	1		T54	1		T138	1
all_values[2]	330511	1		T53	1		T54	1		T138	1
all_values[3]	330511	1		T53	1		T54	1		T138	1
all_values[4]	330511	1		T53	1		T54	1		T138	1
all_values[5]	330511	1		T53	1		T54	1		T138	1

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	10132	1		T53	6		T54	6		T138	6
auto[1]	1972934	1		T197	14		T201	16		T203	17

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1607933	1		T53	6		T54	6		T138	6
auto[1]	375133	1		T197	1		T201	14		T203	7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1235	1		T53	1		T54	1		T138	1
all_values[0]	auto[0]	auto[1]	450	1		T201	2		T203	3		T204	2
all_values[0]	auto[1]	auto[0]	264012	1		T197	1		T203	1		T202	5
all_values[0]	auto[1]	auto[1]	64814	1		T201	2		T204	1		T205	1
all_values[1]	auto[0]	auto[0]	1637	1		T53	1		T54	1		T138	1
all_values[1]	auto[0]	auto[1]	65	1		T197	1		T201	4		T203	2
all_values[1]	auto[1]	auto[0]	280727	1		T197	1		T201	2		T203	3
all_values[1]	auto[1]	auto[1]	48082	1		T202	1		T205	2		T321	1
all_values[2]	auto[0]	auto[0]	1556	1		T53	1		T54	1		T138	1
all_values[2]	auto[0]	auto[1]	126	1		T202	3		T205	1		T329	2
all_values[2]	auto[1]	auto[0]	325180	1		T197	3		T201	5		T203	4
all_values[2]	auto[1]	auto[1]	3649	1		T202	1		T204	4		T205	1
all_values[3]	auto[0]	auto[0]	1547	1		T53	1		T54	1		T138	1
all_values[3]	auto[0]	auto[1]	136	1		T203	1		T204	1		T205	2
all_values[3]	auto[1]	auto[0]	169815	1		T197	3		T201	1		T203	1
all_values[3]	auto[1]	auto[1]	159013	1		T201	2		T202	2		T205	2
all_values[4]	auto[0]	auto[0]	1143	1		T53	1		T54	1		T138	1
all_values[4]	auto[0]	auto[1]	553	1		T201	1		T203	1		T204	1
all_values[4]	auto[1]	auto[0]	230761	1		T197	2		T201	1		T203	4
all_values[4]	auto[1]	auto[1]	98054	1		T202	3		T204	1		T322	1
all_values[5]	auto[0]	auto[0]	1549	1		T53	1		T54	1		T138	1
all_values[5]	auto[0]	auto[1]	135	1		T201	2		T204	2		T205	2
all_values[5]	auto[1]	auto[0]	328771	1		T197	4		T201	2		T203	4
all_values[5]	auto[1]	auto[1]	56	1		T201	1		T202	1		T204	2