Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T16 |
1 |
|
T197 |
1 |
|
T142 |
1 |
| others[1] |
1275 |
1 |
|
T54 |
1 |
|
T203 |
1 |
|
T144 |
1 |
| others[2] |
1226 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T196 |
1 |
| others[3] |
2066 |
1 |
|
T139 |
1 |
|
T321 |
1 |
|
T329 |
1 |
| false |
648 |
1 |
|
T322 |
1 |
|
T9 |
1 |
|
T22 |
10 |
| true |
409 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T29 |
1 |
|
T30 |
6 |
|
T135 |
1 |
| others[1] |
103 |
1 |
|
T29 |
1 |
|
T30 |
3 |
|
T358 |
1 |
| others[2] |
106 |
1 |
|
T30 |
3 |
|
T359 |
1 |
|
T109 |
2 |
| others[3] |
166 |
1 |
|
T235 |
1 |
|
T30 |
5 |
|
T358 |
1 |
| false |
44 |
1 |
|
T30 |
3 |
|
T365 |
1 |
|
T109 |
4 |
| true |
6343 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
261 |
1 |
|
T39 |
2 |
|
T69 |
1 |
|
T59 |
1 |
| others[1] |
233 |
1 |
|
T10 |
1 |
|
T30 |
1 |
|
T363 |
1 |
| others[2] |
225 |
1 |
|
T7 |
1 |
|
T44 |
1 |
|
T47 |
1 |
| others[3] |
422 |
1 |
|
T30 |
5 |
|
T294 |
1 |
|
T213 |
1 |
| false |
110 |
1 |
|
T61 |
1 |
|
T367 |
1 |
|
T109 |
3 |
| true |
5617 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1007 |
1 |
|
T54 |
1 |
|
T142 |
1 |
|
T202 |
1 |
| others[1] |
1076 |
1 |
|
T53 |
1 |
|
T197 |
1 |
|
T203 |
1 |
| others[2] |
1060 |
1 |
|
T141 |
1 |
|
T201 |
1 |
|
T321 |
1 |
| others[3] |
1819 |
1 |
|
T16 |
1 |
|
T196 |
1 |
|
T139 |
1 |
| false |
555 |
1 |
|
T138 |
1 |
|
T34 |
1 |
|
T9 |
2 |
| true |
1351 |
1 |
|
T1 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T7 |
1 |
|
T30 |
1 |
|
T363 |
1 |
| others[1] |
239 |
1 |
|
T39 |
1 |
|
T235 |
1 |
|
T30 |
2 |
| others[2] |
228 |
1 |
|
T30 |
1 |
|
T40 |
1 |
|
T367 |
1 |
| others[3] |
410 |
1 |
|
T10 |
1 |
|
T39 |
1 |
|
T30 |
5 |
| false |
111 |
1 |
|
T47 |
1 |
|
T39 |
1 |
|
T59 |
1 |
| true |
5663 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T30 |
1 |
|
T69 |
1 |
|
T294 |
1 |
| others[1] |
214 |
1 |
|
T39 |
2 |
|
T29 |
1 |
|
T30 |
4 |
| others[2] |
228 |
1 |
|
T30 |
1 |
|
T41 |
1 |
|
T109 |
13 |
| others[3] |
360 |
1 |
|
T5 |
1 |
|
T39 |
1 |
|
T29 |
1 |
| false |
112 |
1 |
|
T30 |
3 |
|
T360 |
1 |
|
T109 |
5 |
| true |
5729 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1206 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T321 |
1 |
| others[1] |
1289 |
1 |
|
T203 |
1 |
|
T144 |
1 |
|
T204 |
1 |
| others[2] |
1237 |
1 |
|
T54 |
1 |
|
T145 |
1 |
|
T205 |
1 |
| others[3] |
2068 |
1 |
|
T196 |
1 |
|
T139 |
1 |
|
T197 |
1 |
| false |
627 |
1 |
|
T16 |
1 |
|
T142 |
1 |
|
T322 |
1 |
| true |
441 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T54 |
1 |
|
T205 |
1 |
|
T322 |
1 |
| others[1] |
1224 |
1 |
|
T141 |
1 |
|
T9 |
3 |
|
T22 |
16 |
| others[2] |
1257 |
1 |
|
T53 |
1 |
|
T196 |
1 |
|
T201 |
1 |
| others[3] |
2094 |
1 |
|
T16 |
1 |
|
T138 |
1 |
|
T197 |
1 |
| false |
628 |
1 |
|
T139 |
1 |
|
T144 |
1 |
|
T9 |
1 |
| true |
424 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T30 |
3 |
|
T136 |
1 |
|
T109 |
6 |
| others[1] |
107 |
1 |
|
T30 |
2 |
|
T358 |
1 |
|
T365 |
1 |
| others[2] |
111 |
1 |
|
T1 |
1 |
|
T29 |
1 |
|
T30 |
7 |
| others[3] |
156 |
1 |
|
T29 |
1 |
|
T30 |
7 |
|
T358 |
1 |
| false |
44 |
1 |
|
T47 |
1 |
|
T30 |
1 |
|
T109 |
1 |
| true |
6344 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
202 |
1 |
|
T30 |
1 |
|
T66 |
1 |
|
T109 |
10 |
| others[1] |
264 |
1 |
|
T24 |
1 |
|
T47 |
1 |
|
T26 |
1 |
| others[2] |
247 |
1 |
|
T29 |
2 |
|
T30 |
2 |
|
T61 |
1 |
| others[3] |
373 |
1 |
|
T1 |
1 |
|
T7 |
1 |
|
T39 |
1 |
| false |
140 |
1 |
|
T39 |
1 |
|
T30 |
3 |
|
T109 |
5 |
| true |
5642 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
993 |
1 |
|
T202 |
1 |
|
T145 |
1 |
|
T35 |
1 |
| others[1] |
1017 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T142 |
1 |
| others[2] |
1089 |
1 |
|
T141 |
1 |
|
T361 |
1 |
|
T205 |
1 |
| others[3] |
1778 |
1 |
|
T16 |
1 |
|
T196 |
1 |
|
T139 |
1 |
| false |
549 |
1 |
|
T54 |
1 |
|
T322 |
1 |
|
T9 |
3 |
| true |
1442 |
1 |
|
T1 |
1 |
|
T44 |
1 |
|
T46 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T39 |
1 |
|
T26 |
1 |
|
T30 |
1 |
| others[1] |
234 |
1 |
|
T47 |
1 |
|
T39 |
1 |
|
T29 |
1 |
| others[2] |
218 |
1 |
|
T30 |
2 |
|
T109 |
13 |
|
T118 |
2 |
| others[3] |
390 |
1 |
|
T5 |
1 |
|
T29 |
1 |
|
T30 |
4 |
| false |
111 |
1 |
|
T10 |
1 |
|
T30 |
1 |
|
T59 |
1 |
| true |
5675 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T30 |
1 |
|
T116 |
1 |
|
T59 |
1 |
| others[1] |
218 |
1 |
|
T30 |
3 |
|
T69 |
1 |
|
T41 |
1 |
| others[2] |
210 |
1 |
|
T30 |
2 |
|
T359 |
1 |
|
T365 |
1 |
| others[3] |
398 |
1 |
|
T47 |
1 |
|
T39 |
1 |
|
T30 |
1 |
| false |
111 |
1 |
|
T39 |
1 |
|
T26 |
1 |
|
T30 |
1 |
| true |
5694 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1246 |
1 |
|
T16 |
1 |
|
T361 |
1 |
|
T205 |
1 |
| others[1] |
1199 |
1 |
|
T139 |
1 |
|
T197 |
1 |
|
T202 |
1 |
| others[2] |
1278 |
1 |
|
T141 |
1 |
|
T142 |
1 |
|
T144 |
1 |
| others[3] |
2057 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T196 |
1 |
| false |
653 |
1 |
|
T54 |
1 |
|
T203 |
1 |
|
T10 |
1 |
| true |
435 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1314 |
1 |
|
T196 |
1 |
|
T202 |
1 |
|
T361 |
1 |
| others[1] |
1223 |
1 |
|
T204 |
1 |
|
T329 |
1 |
|
T9 |
3 |
| others[2] |
1223 |
1 |
|
T141 |
1 |
|
T8 |
1 |
|
T34 |
1 |
| others[3] |
2051 |
1 |
|
T16 |
1 |
|
T54 |
1 |
|
T138 |
1 |
| false |
634 |
1 |
|
T53 |
1 |
|
T139 |
1 |
|
T144 |
1 |
| true |
423 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
87 |
1 |
|
T29 |
1 |
|
T30 |
4 |
|
T358 |
1 |
| others[1] |
109 |
1 |
|
T5 |
1 |
|
T29 |
1 |
|
T30 |
5 |
| others[2] |
106 |
1 |
|
T30 |
2 |
|
T363 |
1 |
|
T358 |
1 |
| others[3] |
167 |
1 |
|
T235 |
1 |
|
T30 |
4 |
|
T365 |
1 |
| false |
53 |
1 |
|
T30 |
5 |
|
T109 |
2 |
|
T214 |
1 |
| true |
6346 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
249 |
1 |
|
T24 |
1 |
|
T30 |
2 |
|
T109 |
12 |
| others[1] |
245 |
1 |
|
T1 |
1 |
|
T26 |
1 |
|
T30 |
2 |
| others[2] |
232 |
1 |
|
T10 |
1 |
|
T39 |
1 |
|
T30 |
3 |
| others[3] |
422 |
1 |
|
T39 |
3 |
|
T235 |
1 |
|
T30 |
3 |
| false |
125 |
1 |
|
T30 |
1 |
|
T67 |
1 |
|
T367 |
1 |
| true |
5595 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1086 |
1 |
|
T16 |
1 |
|
T144 |
1 |
|
T204 |
1 |
| others[1] |
1049 |
1 |
|
T138 |
1 |
|
T141 |
1 |
|
T142 |
1 |
| others[2] |
1045 |
1 |
|
T202 |
1 |
|
T322 |
1 |
|
T9 |
3 |
| others[3] |
1745 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T196 |
1 |
| false |
565 |
1 |
|
T9 |
3 |
|
T22 |
9 |
|
T45 |
1 |
| true |
1378 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T39 |
1 |
|
T30 |
2 |
|
T68 |
1 |
| others[1] |
230 |
1 |
|
T39 |
1 |
|
T30 |
1 |
|
T359 |
1 |
| others[2] |
217 |
1 |
|
T39 |
2 |
|
T40 |
1 |
|
T247 |
1 |
| others[3] |
358 |
1 |
|
T46 |
1 |
|
T30 |
1 |
|
T294 |
1 |
| false |
111 |
1 |
|
T5 |
1 |
|
T235 |
1 |
|
T30 |
2 |
| true |
5739 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T39 |
1 |
|
T235 |
1 |
|
T30 |
2 |
| others[1] |
225 |
1 |
|
T30 |
3 |
|
T360 |
1 |
|
T109 |
6 |
| others[2] |
225 |
1 |
|
T30 |
1 |
|
T363 |
1 |
|
T360 |
1 |
| others[3] |
359 |
1 |
|
T5 |
1 |
|
T30 |
2 |
|
T112 |
1 |
| false |
117 |
1 |
|
T109 |
6 |
|
T118 |
4 |
|
T127 |
4 |
| true |
5713 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T141 |
1 |
|
T201 |
1 |
|
T203 |
1 |
| others[1] |
1247 |
1 |
|
T54 |
1 |
|
T138 |
1 |
|
T145 |
1 |
| others[2] |
1209 |
1 |
|
T16 |
1 |
|
T197 |
1 |
|
T142 |
1 |
| others[3] |
2093 |
1 |
|
T53 |
1 |
|
T196 |
1 |
|
T205 |
1 |
| false |
622 |
1 |
|
T139 |
1 |
|
T144 |
1 |
|
T8 |
1 |
| true |
449 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1258 |
1 |
|
T141 |
1 |
|
T202 |
1 |
|
T204 |
1 |
| others[1] |
1205 |
1 |
|
T53 |
1 |
|
T142 |
1 |
|
T361 |
1 |
| others[2] |
1267 |
1 |
|
T54 |
1 |
|
T196 |
1 |
|
T144 |
1 |
| others[3] |
2099 |
1 |
|
T16 |
1 |
|
T138 |
1 |
|
T139 |
1 |
| false |
627 |
1 |
|
T201 |
1 |
|
T203 |
1 |
|
T9 |
3 |
| true |
412 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T30 |
4 |
|
T359 |
1 |
|
T109 |
4 |
| others[1] |
108 |
1 |
|
T30 |
7 |
|
T40 |
1 |
|
T109 |
4 |
| others[2] |
91 |
1 |
|
T5 |
1 |
|
T47 |
1 |
|
T30 |
4 |
| others[3] |
174 |
1 |
|
T29 |
2 |
|
T30 |
3 |
|
T112 |
1 |
| false |
61 |
1 |
|
T46 |
1 |
|
T30 |
2 |
|
T136 |
1 |
| true |
6321 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T30 |
1 |
|
T216 |
1 |
|
T365 |
1 |
| others[1] |
230 |
1 |
|
T10 |
1 |
|
T47 |
1 |
|
T30 |
5 |
| others[2] |
252 |
1 |
|
T1 |
1 |
|
T44 |
1 |
|
T26 |
1 |
| others[3] |
393 |
1 |
|
T24 |
1 |
|
T46 |
1 |
|
T39 |
1 |
| false |
118 |
1 |
|
T5 |
1 |
|
T235 |
1 |
|
T30 |
2 |
| true |
5631 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1066 |
1 |
|
T16 |
1 |
|
T142 |
1 |
|
T205 |
1 |
| others[1] |
1067 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T197 |
1 |
| others[2] |
1093 |
1 |
|
T196 |
1 |
|
T139 |
1 |
|
T141 |
1 |
| others[3] |
1754 |
1 |
|
T138 |
1 |
|
T144 |
1 |
|
T204 |
1 |
| false |
529 |
1 |
|
T35 |
1 |
|
T9 |
1 |
|
T22 |
9 |
| true |
1359 |
1 |
|
T10 |
1 |
|
T7 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T7 |
1 |
|
T29 |
1 |
|
T30 |
2 |
| others[1] |
222 |
1 |
|
T24 |
1 |
|
T39 |
1 |
|
T235 |
1 |
| others[2] |
185 |
1 |
|
T30 |
1 |
|
T40 |
1 |
|
T135 |
1 |
| others[3] |
371 |
1 |
|
T39 |
1 |
|
T29 |
1 |
|
T30 |
2 |
| false |
119 |
1 |
|
T5 |
1 |
|
T39 |
1 |
|
T30 |
1 |
| true |
5742 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T39 |
1 |
|
T29 |
1 |
|
T30 |
1 |
| others[1] |
221 |
1 |
|
T39 |
1 |
|
T30 |
2 |
|
T109 |
2 |
| others[2] |
228 |
1 |
|
T5 |
1 |
|
T30 |
2 |
|
T112 |
1 |
| others[3] |
367 |
1 |
|
T39 |
1 |
|
T30 |
5 |
|
T40 |
1 |
| false |
117 |
1 |
|
T30 |
3 |
|
T247 |
1 |
|
T109 |
5 |
| true |
5734 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T139 |
1 |
|
T203 |
1 |
|
T202 |
1 |
| others[1] |
1247 |
1 |
|
T16 |
1 |
|
T138 |
1 |
|
T8 |
1 |
| others[2] |
1243 |
1 |
|
T204 |
1 |
|
T335 |
1 |
|
T9 |
3 |
| others[3] |
2047 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T196 |
1 |
| false |
662 |
1 |
|
T144 |
1 |
|
T145 |
1 |
|
T1 |
1 |
| true |
438 |
1 |
|
T10 |
1 |
|
T5 |
1 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
13 |
1 |
|
T159 |
1 |
|
T177 |
1 |
|
T172 |
1 |
| others[1] |
11 |
1 |
|
T85 |
1 |
|
T76 |
1 |
|
T173 |
1 |
| others[2] |
6 |
1 |
|
T27 |
1 |
|
T369 |
1 |
|
T370 |
1 |
| others[3] |
8 |
1 |
|
T3 |
1 |
|
T75 |
1 |
|
T371 |
1 |
| false |
1 |
1 |
|
T372 |
1 |
|
- |
- |
|
- |
- |
| true |
51 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T84 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T304 |
1 |
|
T373 |
1 |
|
- |
- |
| others[1] |
2 |
1 |
|
T374 |
1 |
|
T375 |
1 |
|
- |
- |
| others[2] |
2 |
1 |
|
T25 |
1 |
|
T376 |
1 |
|
- |
- |
| others[3] |
3 |
1 |
|
T186 |
1 |
|
T377 |
1 |
|
T378 |
1 |
| false |
12 |
1 |
|
T379 |
1 |
|
T380 |
1 |
|
T381 |
1 |
| true |
27 |
1 |
|
T4 |
1 |
|
T62 |
1 |
|
T81 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T376 |
1 |
|
T375 |
1 |
|
T382 |
1 |
| others[1] |
2 |
1 |
|
T62 |
1 |
|
T383 |
1 |
|
- |
- |
| others[2] |
4 |
1 |
|
T384 |
1 |
|
T385 |
1 |
|
T386 |
1 |
| others[3] |
4 |
1 |
|
T4 |
1 |
|
T186 |
1 |
|
T387 |
1 |
| false |
8 |
1 |
|
T388 |
1 |
|
T389 |
1 |
|
T373 |
1 |
| true |
25 |
1 |
|
T25 |
1 |
|
T81 |
1 |
|
T304 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |