Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9050 |
1 |
|
T16 |
1 |
|
T322 |
1 |
|
T2 |
2 |
| others[1] |
459 |
1 |
|
T144 |
1 |
|
T34 |
1 |
|
T9 |
3 |
| others[2] |
467 |
1 |
|
T201 |
1 |
|
T204 |
1 |
|
T329 |
1 |
| others[3] |
810 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T142 |
1 |
| false |
255 |
1 |
|
T139 |
1 |
|
T321 |
1 |
|
T7 |
1 |
| true |
2126 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T196 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8871 |
1 |
|
T141 |
1 |
|
T361 |
1 |
|
T2 |
2 |
| others[1] |
277 |
1 |
|
T139 |
1 |
|
T197 |
1 |
|
T322 |
1 |
| others[2] |
242 |
1 |
|
T16 |
1 |
|
T138 |
1 |
|
T196 |
1 |
| others[3] |
434 |
1 |
|
T46 |
1 |
|
T39 |
2 |
|
T58 |
1 |
| false |
140 |
1 |
|
T1 |
1 |
|
T59 |
1 |
|
T247 |
1 |
| true |
3203 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T142 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8848 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T205 |
1 |
| others[1] |
271 |
1 |
|
T196 |
1 |
|
T321 |
1 |
|
T47 |
1 |
| others[2] |
234 |
1 |
|
T16 |
1 |
|
T201 |
1 |
|
T34 |
1 |
| others[3] |
400 |
1 |
|
T138 |
1 |
|
T39 |
1 |
|
T104 |
1 |
| false |
137 |
1 |
|
T45 |
1 |
|
T30 |
3 |
|
T65 |
1 |
| true |
3277 |
1 |
|
T53 |
1 |
|
T139 |
1 |
|
T197 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9375 |
1 |
|
T141 |
1 |
|
T201 |
1 |
|
T335 |
1 |
| others[1] |
799 |
1 |
|
T53 |
1 |
|
T197 |
1 |
|
T202 |
1 |
| others[2] |
776 |
1 |
|
T145 |
1 |
|
T321 |
1 |
|
T10 |
1 |
| others[3] |
1323 |
1 |
|
T16 |
1 |
|
T54 |
1 |
|
T196 |
1 |
| false |
407 |
1 |
|
T138 |
1 |
|
T142 |
1 |
|
T322 |
1 |
| true |
487 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T35 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9405 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[1] |
791 |
1 |
|
T196 |
1 |
|
T197 |
1 |
|
T141 |
1 |
| others[2] |
742 |
1 |
|
T322 |
1 |
|
T335 |
1 |
|
T9 |
5 |
| others[3] |
1284 |
1 |
|
T139 |
1 |
|
T203 |
1 |
|
T202 |
1 |
| false |
431 |
1 |
|
T138 |
1 |
|
T205 |
1 |
|
T34 |
1 |
| true |
514 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2192 |
1 |
|
T142 |
1 |
|
T203 |
1 |
|
T202 |
1 |
| others[1] |
2264 |
1 |
|
T16 |
1 |
|
T141 |
1 |
|
T144 |
1 |
| others[2] |
2262 |
1 |
|
T196 |
1 |
|
T204 |
1 |
|
T5 |
1 |
| others[3] |
3819 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T139 |
1 |
| false |
1117 |
1 |
|
T54 |
1 |
|
T2 |
1 |
|
T84 |
1 |
| true |
1513 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8814 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
| others[1] |
279 |
1 |
|
T203 |
1 |
|
T1 |
1 |
|
T30 |
2 |
| others[2] |
259 |
1 |
|
T139 |
1 |
|
T202 |
1 |
|
T5 |
1 |
| others[3] |
439 |
1 |
|
T201 |
1 |
|
T329 |
1 |
|
T8 |
1 |
| false |
142 |
1 |
|
T197 |
1 |
|
T141 |
1 |
|
T26 |
1 |
| true |
3234 |
1 |
|
T138 |
1 |
|
T196 |
1 |
|
T142 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9037 |
1 |
|
T142 |
1 |
|
T144 |
1 |
|
T204 |
1 |
| others[1] |
480 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T321 |
1 |
| others[2] |
467 |
1 |
|
T197 |
1 |
|
T145 |
1 |
|
T205 |
1 |
| others[3] |
780 |
1 |
|
T54 |
1 |
|
T9 |
2 |
|
T22 |
19 |
| false |
232 |
1 |
|
T9 |
2 |
|
T22 |
2 |
|
T44 |
1 |
| true |
2171 |
1 |
|
T138 |
1 |
|
T196 |
1 |
|
T139 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8838 |
1 |
|
T204 |
1 |
|
T205 |
1 |
|
T2 |
2 |
| others[1] |
232 |
1 |
|
T141 |
1 |
|
T203 |
1 |
|
T335 |
1 |
| others[2] |
264 |
1 |
|
T322 |
1 |
|
T39 |
2 |
|
T30 |
1 |
| others[3] |
436 |
1 |
|
T197 |
1 |
|
T201 |
1 |
|
T44 |
1 |
| false |
140 |
1 |
|
T196 |
1 |
|
T7 |
1 |
|
T30 |
2 |
| true |
3257 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8843 |
1 |
|
T53 |
1 |
|
T204 |
1 |
|
T2 |
2 |
| others[1] |
261 |
1 |
|
T197 |
1 |
|
T203 |
1 |
|
T321 |
1 |
| others[2] |
251 |
1 |
|
T335 |
1 |
|
T1 |
1 |
|
T46 |
1 |
| others[3] |
388 |
1 |
|
T54 |
1 |
|
T142 |
1 |
|
T144 |
1 |
| false |
141 |
1 |
|
T201 |
1 |
|
T113 |
1 |
|
T41 |
1 |
| true |
3283 |
1 |
|
T16 |
1 |
|
T138 |
1 |
|
T196 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9374 |
1 |
|
T16 |
1 |
|
T54 |
1 |
|
T205 |
1 |
| others[1] |
809 |
1 |
|
T53 |
1 |
|
T196 |
1 |
|
T321 |
1 |
| others[2] |
766 |
1 |
|
T203 |
1 |
|
T144 |
1 |
|
T204 |
1 |
| others[3] |
1297 |
1 |
|
T138 |
1 |
|
T197 |
1 |
|
T141 |
1 |
| false |
426 |
1 |
|
T139 |
1 |
|
T142 |
1 |
|
T202 |
1 |
| true |
495 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9345 |
1 |
|
T54 |
1 |
|
T2 |
2 |
|
T84 |
2 |
| others[1] |
750 |
1 |
|
T16 |
1 |
|
T142 |
1 |
|
T201 |
1 |
| others[2] |
777 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T144 |
1 |
| others[3] |
1357 |
1 |
|
T139 |
1 |
|
T197 |
1 |
|
T141 |
1 |
| false |
409 |
1 |
|
T196 |
1 |
|
T22 |
7 |
|
T190 |
1 |
| true |
529 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2298 |
1 |
|
T196 |
1 |
|
T197 |
1 |
|
T2 |
2 |
| others[1] |
2299 |
1 |
|
T54 |
1 |
|
T142 |
1 |
|
T201 |
1 |
| others[2] |
2215 |
1 |
|
T53 |
1 |
|
T203 |
1 |
|
T329 |
1 |
| others[3] |
3700 |
1 |
|
T16 |
1 |
|
T138 |
1 |
|
T139 |
1 |
| false |
1120 |
1 |
|
T141 |
1 |
|
T205 |
1 |
|
T321 |
1 |
| true |
1535 |
1 |
|
T6 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8829 |
1 |
|
T2 |
2 |
|
T7 |
1 |
|
T84 |
2 |
| others[1] |
263 |
1 |
|
T16 |
1 |
|
T197 |
1 |
|
T34 |
1 |
| others[2] |
250 |
1 |
|
T1 |
1 |
|
T30 |
1 |
|
T63 |
1 |
| others[3] |
464 |
1 |
|
T138 |
1 |
|
T139 |
1 |
|
T142 |
1 |
| false |
133 |
1 |
|
T54 |
1 |
|
T141 |
1 |
|
T201 |
1 |
| true |
3228 |
1 |
|
T53 |
1 |
|
T196 |
1 |
|
T203 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9043 |
1 |
|
T53 |
1 |
|
T2 |
2 |
|
T84 |
2 |
| others[1] |
497 |
1 |
|
T139 |
1 |
|
T202 |
1 |
|
T321 |
1 |
| others[2] |
466 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T9 |
2 |
| others[3] |
729 |
1 |
|
T138 |
1 |
|
T141 |
1 |
|
T201 |
1 |
| false |
260 |
1 |
|
T196 |
1 |
|
T197 |
1 |
|
T203 |
1 |
| true |
2172 |
1 |
|
T16 |
1 |
|
T54 |
1 |
|
T142 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8832 |
1 |
|
T202 |
1 |
|
T2 |
2 |
|
T5 |
1 |
| others[1] |
269 |
1 |
|
T54 |
1 |
|
T361 |
1 |
|
T329 |
1 |
| others[2] |
283 |
1 |
|
T16 |
1 |
|
T145 |
1 |
|
T46 |
1 |
| others[3] |
440 |
1 |
|
T139 |
1 |
|
T8 |
1 |
|
T44 |
1 |
| false |
150 |
1 |
|
T201 |
1 |
|
T205 |
1 |
|
T30 |
1 |
| true |
3193 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T196 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8851 |
1 |
|
T53 |
1 |
|
T197 |
1 |
|
T141 |
1 |
| others[1] |
253 |
1 |
|
T45 |
1 |
|
T39 |
1 |
|
T30 |
4 |
| others[2] |
259 |
1 |
|
T16 |
1 |
|
T144 |
1 |
|
T145 |
1 |
| others[3] |
440 |
1 |
|
T139 |
1 |
|
T329 |
1 |
|
T8 |
1 |
| false |
121 |
1 |
|
T196 |
1 |
|
T203 |
1 |
|
T108 |
1 |
| true |
3243 |
1 |
|
T54 |
1 |
|
T138 |
1 |
|
T142 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9366 |
1 |
|
T202 |
1 |
|
T361 |
1 |
|
T335 |
1 |
| others[1] |
807 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T196 |
1 |
| others[2] |
801 |
1 |
|
T16 |
1 |
|
T205 |
1 |
|
T9 |
5 |
| others[3] |
1288 |
1 |
|
T197 |
1 |
|
T142 |
1 |
|
T144 |
1 |
| false |
408 |
1 |
|
T54 |
1 |
|
T139 |
1 |
|
T203 |
1 |
| true |
497 |
1 |
|
T6 |
1 |
|
T10 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9320 |
1 |
|
T16 |
1 |
|
T53 |
1 |
|
T139 |
1 |
| others[1] |
825 |
1 |
|
T196 |
1 |
|
T201 |
1 |
|
T203 |
1 |
| others[2] |
742 |
1 |
|
T197 |
1 |
|
T141 |
1 |
|
T9 |
6 |
| others[3] |
1334 |
1 |
|
T54 |
1 |
|
T142 |
1 |
|
T204 |
1 |
| false |
425 |
1 |
|
T138 |
1 |
|
T9 |
3 |
|
T22 |
10 |
| true |
521 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2226 |
1 |
|
T54 |
1 |
|
T203 |
1 |
|
T145 |
1 |
| others[1] |
2352 |
1 |
|
T16 |
1 |
|
T196 |
1 |
|
T139 |
1 |
| others[2] |
2142 |
1 |
|
T201 |
1 |
|
T361 |
1 |
|
T205 |
1 |
| others[3] |
3776 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T197 |
1 |
| false |
1153 |
1 |
|
T144 |
1 |
|
T84 |
1 |
|
T22 |
7 |
| true |
1518 |
1 |
|
T1 |
1 |
|
T6 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8848 |
1 |
|
T53 |
1 |
|
T203 |
1 |
|
T144 |
1 |
| others[1] |
270 |
1 |
|
T139 |
1 |
|
T204 |
1 |
|
T1 |
1 |
| others[2] |
247 |
1 |
|
T196 |
1 |
|
T141 |
1 |
|
T205 |
1 |
| others[3] |
486 |
1 |
|
T145 |
1 |
|
T322 |
1 |
|
T47 |
1 |
| false |
143 |
1 |
|
T30 |
3 |
|
T61 |
1 |
|
T63 |
1 |
| true |
3173 |
1 |
|
T16 |
1 |
|
T54 |
1 |
|
T138 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9009 |
1 |
|
T16 |
1 |
|
T138 |
1 |
|
T204 |
1 |
| others[1] |
456 |
1 |
|
T139 |
1 |
|
T322 |
1 |
|
T335 |
1 |
| others[2] |
483 |
1 |
|
T361 |
1 |
|
T9 |
4 |
|
T22 |
12 |
| others[3] |
779 |
1 |
|
T54 |
1 |
|
T196 |
1 |
|
T197 |
1 |
| false |
247 |
1 |
|
T9 |
2 |
|
T22 |
5 |
|
T30 |
3 |
| true |
2193 |
1 |
|
T53 |
1 |
|
T142 |
1 |
|
T201 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8847 |
1 |
|
T196 |
1 |
|
T197 |
1 |
|
T142 |
1 |
| others[1] |
261 |
1 |
|
T53 |
1 |
|
T138 |
1 |
|
T139 |
1 |
| others[2] |
261 |
1 |
|
T47 |
1 |
|
T29 |
1 |
|
T26 |
1 |
| others[3] |
441 |
1 |
|
T361 |
1 |
|
T205 |
1 |
|
T1 |
1 |
| false |
128 |
1 |
|
T10 |
1 |
|
T30 |
1 |
|
T105 |
1 |
| true |
3229 |
1 |
|
T16 |
1 |
|
T54 |
1 |
|
T141 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8837 |
1 |
|
T2 |
2 |
|
T84 |
2 |
|
T23 |
160 |
| others[1] |
243 |
1 |
|
T138 |
1 |
|
T321 |
1 |
|
T47 |
1 |
| others[2] |
235 |
1 |
|
T142 |
1 |
|
T361 |
1 |
|
T205 |
1 |
| others[3] |
435 |
1 |
|
T53 |
1 |
|
T54 |
1 |
|
T197 |
1 |
| false |
128 |
1 |
|
T201 |
1 |
|
T29 |
1 |
|
T115 |
1 |
| true |
3289 |
1 |
|
T16 |
1 |
|
T196 |
1 |
|
T139 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9332 |
1 |
|
T53 |
1 |
|
T197 |
1 |
|
T203 |
1 |
| others[1] |
807 |
1 |
|
T16 |
1 |
|
T201 |
1 |
|
T9 |
3 |
| others[2] |
803 |
1 |
|
T139 |
1 |
|
T202 |
1 |
|
T144 |
1 |
| others[3] |
1296 |
1 |
|
T54 |
1 |
|
T138 |
1 |
|
T196 |
1 |
| false |
434 |
1 |
|
T9 |
1 |
|
T22 |
7 |
|
T30 |
2 |
| true |
495 |
1 |
|
T6 |
1 |
|
T5 |
1 |
|
T35 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |