Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	219931	1		T1	1383		T2	1		T4	247
auto[FlashEraseBank]	200353	1		T1	1555		T10	15		T5	251

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	232327	1		T1	1195		T2	1		T4	12
auto[FlashOpProgram]	169548	1		T1	1743		T4	224		T5	306
auto[FlashOpErase]	14409	1		T4	11		T10	39		T9	5
auto[FlashOpInvalid]	4000	1		T131	200		T103	200		T228	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	232327	1		T1	1195		T2	1		T4	12
op[FlashOpProgram]	169548	1		T1	1743		T4	224		T5	306
op[FlashOpErase]	14409	1		T4	11		T10	39		T9	5
read_erase_read	769	1		T4	2		T10	19		T9	2
read_prog_read	1245	1		T1	5		T5	4		T7	28

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	288575	1		T1	2279		T10	29		T5	474
auto[FlashPartInfo]	128437	1		T1	646		T2	1		T4	247
auto[FlashPartInfo1]	631	1		T1	2		T5	2		T8	2
auto[FlashPartInfo2]	2641	1		T1	11		T5	2		T8	6

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	173258	1		T1	894		T10	9		T5	248
auto[FlashPartData]	auto[FlashOpProgram]	107742	1		T1	1385		T5	226		T7	7
auto[FlashPartData]	auto[FlashOpErase]	3663	1		T10	20		T9	5		T30	2
auto[FlashPartData]	auto[FlashOpInvalid]	3912	1		T131	194		T103	198		T228	194
auto[FlashPartInfo]	auto[FlashOpRead]	56933	1		T1	294		T2	1		T4	12
auto[FlashPartInfo]	auto[FlashOpProgram]	60704	1		T1	352		T4	224		T5	78
auto[FlashPartInfo]	auto[FlashOpErase]	10724	1		T4	11		T10	19		T25	12
auto[FlashPartInfo]	auto[FlashOpInvalid]	76	1		T131	4		T103	2		T228	6
auto[FlashPartInfo1]	auto[FlashOpRead]	558	1		T1	2		T5	2		T8	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	67	1		T87	32		T88	1		T92	1
auto[FlashPartInfo1]	auto[FlashOpErase]	2	1		T92	1		T391	1		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	4	1		T92	2		T391	2		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1578	1		T1	5		T8	6		T45	4
auto[FlashPartInfo2]	auto[FlashOpProgram]	1035	1		T1	6		T5	2		T45	5
auto[FlashPartInfo2]	auto[FlashOpErase]	20	1		T107	1		T131	1		T86	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T131	2		T392	2		T393	2