Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27422	1		T9	1		T23	456		T45	1
auto[1]	18	1		T216	1		T99	3		T208	1
auto[2]	253	1		T110	3		T154	8		T368	35
auto[3]	264	1		T61	2		T66	1		T67	1

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7008	1		T9	1		T23	114		T61	1
evic_idx[1]	7002	1		T23	114		T61	1		T79	1
evic_idx[2]	6978	1		T23	114		T79	1		T81	1
evic_idx[3]	6969	1		T23	114		T45	1		T79	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	26965	1		T23	456		T79	4		T81	4
evic_op[2]	464	1		T9	1		T45	1		T61	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6676	1		T23	114		T79	1		T81	1
evic_idx[0]	evic_op[1]	auto[1]	1	1		T394	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[2]	10	1		T368	10		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	66	1		T222	10		T395	9		T396	6
evic_idx[0]	evic_op[2]	auto[0]	51	1		T9	1		T70	1		T83	2
evic_idx[0]	evic_op[2]	auto[1]	1	1		T208	1		-	-		-	-
evic_idx[0]	evic_op[2]	auto[2]	56	1		T397	6		T297	1		T398	4
evic_idx[0]	evic_op[2]	auto[3]	15	1		T61	1		T66	1		T213	1
evic_idx[1]	evic_op[1]	auto[0]	6679	1		T23	114		T79	1		T81	1
evic_idx[1]	evic_op[1]	auto[1]	1	1		T394	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[2]	8	1		T368	8		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	65	1		T222	8		T395	7		T396	5
evic_idx[1]	evic_op[2]	auto[0]	55	1		T83	2		T109	1		T223	1
evic_idx[1]	evic_op[2]	auto[1]	4	1		T99	1		T399	1		T188	1
evic_idx[1]	evic_op[2]	auto[2]	49	1		T208	1		T397	4		T297	1
evic_idx[1]	evic_op[2]	auto[3]	9	1		T61	1		T400	1		T401	1
evic_idx[2]	evic_op[1]	auto[0]	6676	1		T23	114		T79	1		T81	1
evic_idx[2]	evic_op[1]	auto[1]	3	1		T394	3		-	-		-	-
evic_idx[2]	evic_op[1]	auto[2]	10	1		T368	10		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	47	1		T222	5		T395	7		T396	5
evic_idx[2]	evic_op[2]	auto[0]	54	1		T83	2		T109	1		T402	1
evic_idx[2]	evic_op[2]	auto[1]	3	1		T99	1		T403	1		T404	1
evic_idx[2]	evic_op[2]	auto[2]	43	1		T110	2		T208	1		T209	1
evic_idx[2]	evic_op[2]	auto[3]	10	1		T67	1		T111	1		T405	1
evic_idx[3]	evic_op[1]	auto[0]	6675	1		T23	114		T79	1		T81	1
evic_idx[3]	evic_op[1]	auto[1]	2	1		T394	2		-	-		-	-
evic_idx[3]	evic_op[1]	auto[2]	7	1		T368	7		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	39	1		T222	6		T395	5		T396	4
evic_idx[3]	evic_op[2]	auto[0]	56	1		T45	1		T83	2		T109	1
evic_idx[3]	evic_op[2]	auto[1]	3	1		T216	1		T99	1		T406	1
evic_idx[3]	evic_op[2]	auto[2]	42	1		T110	1		T209	1		T397	12
evic_idx[3]	evic_op[2]	auto[3]	13	1		T223	1		T405	1		T296	1