Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	0	3	100.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for prog_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
prog_lvl[1]	35815	1		T58	5825		T59	1690		T60	2218
prog_lvl[2]	2806	1		T59	844		T60	216		T407	827
prog_lvl[3]	3	1		T59	1		T407	1		T408	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	5371	1		T44	1		T65	1567		T64	49
rd_lvl[2]	25680	1		T24	6		T44	15		T65	807
rd_lvl[3]	20432	1		T24	12		T44	13		T64	6
rd_lvl[4]	18717	1		T24	31		T44	11		T64	7
rd_lvl[5]	14251	1		T44	338		T64	2		T98	8
rd_lvl[6]	13390	1		T64	2		T98	3		T130	885
rd_lvl[7]	16057	1		T64	848		T98	175		T409	6
rd_lvl[8]	11749	1		T64	1192		T128	2		T410	1400
rd_lvl[9]	4027	1		T411	400		T64	61		T98	257
rd_lvl[10]	7315	1		T411	416		T98	734		T303	34
rd_lvl[11]	5840	1		T44	558		T64	1		T412	466
rd_lvl[12]	4019	1		T24	573		T44	397		T64	2
rd_lvl[13]	2765	1		T24	490		T98	14		T413	937
rd_lvl[14]	2457	1		T366	619		T414	3		T415	810
rd_lvl[15]	3271	1		T44	71		T63	556		T366	495