Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	330511	1		T53	1		T54	1		T138	1
all_pins[1]	330511	1		T53	1		T54	1		T138	1
all_pins[2]	330511	1		T53	1		T54	1		T138	1
all_pins[3]	330511	1		T53	1		T54	1		T138	1
all_pins[4]	330511	1		T53	1		T54	1		T138	1
all_pins[5]	330511	1		T53	1		T54	1		T138	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1607556	1		T53	6		T54	6		T138	6
values[0x1]	375510	1		T201	5		T202	8		T204	8
transitions[0x0=>0x1]	352151	1		T201	5		T202	4		T204	7
transitions[0x1=>0x0]	352154	1		T201	5		T202	5		T204	7

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	265697	1		T53	1		T54	1		T138	1
all_pins[0]	values[0x1]	64814	1		T201	2		T204	1		T205	1
all_pins[0]	transitions[0x0=>0x1]	64789	1		T201	2		T204	1		T205	1
all_pins[0]	transitions[0x1=>0x0]	48057	1		T202	1		T205	2		T321	1
all_pins[1]	values[0x0]	282429	1		T53	1		T54	1		T138	1
all_pins[1]	values[0x1]	48082	1		T202	1		T205	2		T321	1
all_pins[1]	transitions[0x0=>0x1]	48070	1		T205	2		T321	1		T329	5
all_pins[1]	transitions[0x1=>0x0]	5191	1		T204	4		T205	1		T44	71
all_pins[2]	values[0x0]	325308	1		T53	1		T54	1		T138	1
all_pins[2]	values[0x1]	5203	1		T202	1		T204	4		T205	1
all_pins[2]	transitions[0x0=>0x1]	3550	1		T202	1		T204	4		T205	1
all_pins[2]	transitions[0x1=>0x0]	157360	1		T201	2		T202	2		T205	2
all_pins[3]	values[0x0]	171498	1		T53	1		T54	1		T138	1
all_pins[3]	values[0x1]	159013	1		T201	2		T202	2		T205	2
all_pins[3]	transitions[0x0=>0x1]	137374	1		T201	2		T205	2		T321	2
all_pins[3]	transitions[0x1=>0x0]	76703	1		T202	1		T204	1		T335	3
all_pins[4]	values[0x0]	232169	1		T53	1		T54	1		T138	1
all_pins[4]	values[0x1]	98342	1		T202	3		T204	1		T322	1
all_pins[4]	transitions[0x0=>0x1]	98333	1		T202	3		T204	1		T322	1
all_pins[4]	transitions[0x1=>0x0]	47	1		T201	1		T202	1		T204	2
all_pins[5]	values[0x0]	330455	1		T53	1		T54	1		T138	1
all_pins[5]	values[0x1]	56	1		T201	1		T202	1		T204	2
all_pins[5]	transitions[0x0=>0x1]	35	1		T201	1		T204	1		T205	1
all_pins[5]	transitions[0x1=>0x0]	64796	1		T201	2		T335	1		T58	2317