Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	271	1		T197	4		T201	7		T203	4
all_values[1]	271	1		T197	4		T201	7		T203	4
all_values[2]	271	1		T197	4		T201	7		T203	4
all_values[3]	271	1		T197	4		T201	7		T203	4
all_values[4]	271	1		T197	4		T201	7		T203	4
all_values[5]	271	1		T197	4		T201	7		T203	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	894	1		T197	8		T201	24		T203	18
auto[1]	732	1		T197	16		T201	18		T203	6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	656	1		T197	17		T201	21		T203	13
auto[1]	970	1		T197	7		T201	21		T203	11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	964	1		T197	18		T201	26		T203	15
auto[1]	662	1		T197	6		T201	16		T203	9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	0	36	100.00
Automatically Generated Cross Bins	36	0	36	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	47	1		T197	1		T201	2		T203	1
all_values[0]	auto[0]	auto[0]	auto[1]	31	1		T201	1		T203	1		T204	1
all_values[0]	auto[0]	auto[1]	auto[0]	49	1		T197	1		T201	1		T202	3
all_values[0]	auto[0]	auto[1]	auto[1]	25	1		T336	1		T337	1		T338	1
all_values[0]	auto[1]	auto[0]	auto[1]	66	1		T197	1		T201	2		T203	2
all_values[0]	auto[1]	auto[1]	auto[1]	53	1		T197	1		T201	1		T204	2
all_values[1]	auto[0]	auto[0]	auto[0]	68	1		T197	1		T201	1		T202	1
all_values[1]	auto[0]	auto[0]	auto[1]	29	1		T197	1		T201	2		T203	1
all_values[1]	auto[0]	auto[1]	auto[0]	44	1		T201	2		T203	1		T205	2
all_values[1]	auto[0]	auto[1]	auto[1]	23	1		T205	1		T329	3		T339	1
all_values[1]	auto[1]	auto[0]	auto[1]	54	1		T197	1		T201	2		T203	2
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T197	1		T202	1		T321	2
all_values[2]	auto[0]	auto[0]	auto[0]	67	1		T197	1		T201	2		T205	3
all_values[2]	auto[0]	auto[0]	auto[1]	19	1		T202	2		T205	1		T329	1
all_values[2]	auto[0]	auto[1]	auto[0]	63	1		T197	3		T201	4		T203	3
all_values[2]	auto[0]	auto[1]	auto[1]	27	1		T202	1		T204	3		T340	1
all_values[2]	auto[1]	auto[0]	auto[1]	60	1		T203	1		T202	1		T205	2
all_values[2]	auto[1]	auto[1]	auto[1]	35	1		T201	1		T204	1		T321	1
all_values[3]	auto[0]	auto[0]	auto[0]	59	1		T197	1		T201	1		T203	2
all_values[3]	auto[0]	auto[0]	auto[1]	25	1		T201	1		T204	1		T205	2
all_values[3]	auto[0]	auto[1]	auto[0]	51	1		T197	3		T201	2		T205	1
all_values[3]	auto[0]	auto[1]	auto[1]	29	1		T202	1		T205	1		T321	1
all_values[3]	auto[1]	auto[0]	auto[1]	63	1		T201	2		T203	2		T202	1
all_values[3]	auto[1]	auto[1]	auto[1]	44	1		T201	1		T202	1		T329	3
all_values[4]	auto[0]	auto[0]	auto[0]	48	1		T197	1		T201	1		T203	1
all_values[4]	auto[0]	auto[0]	auto[1]	31	1		T205	2		T322	1		T329	1
all_values[4]	auto[0]	auto[1]	auto[0]	43	1		T197	2		T201	2		T203	1
all_values[4]	auto[0]	auto[1]	auto[1]	24	1		T202	2		T335	2		T340	1
all_values[4]	auto[1]	auto[0]	auto[1]	80	1		T201	4		T203	2		T204	2
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T197	1		T202	1		T204	1
all_values[5]	auto[0]	auto[0]	auto[0]	67	1		T201	1		T203	3		T205	1
all_values[5]	auto[0]	auto[0]	auto[1]	19	1		T204	1		T205	1		T329	2
all_values[5]	auto[0]	auto[1]	auto[0]	50	1		T197	3		T201	2		T203	1
all_values[5]	auto[0]	auto[1]	auto[1]	26	1		T201	1		T204	1		T205	1
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T201	2		T202	1		T204	2
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T197	1		T201	1		T202	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal